stxxtc.c

OMAP2530 uboot source code

	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
	CS_0000 | GPL4_1111 | GPL5_1111,
	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,

	/* WBS */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/* UPT */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,

	/* EXC */
	CS_0001 | LAST,
	_NOT_USED_,

	/* REG */
	CS_1110 ,
	CS_0001 | LAST,
};

/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)

/* 9 */
#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

void check_ram(unsigned int addr, unsigned int size)
{
	unsigned int i, j, v, vv;
	volatile unsigned int *p;
	unsigned int pv;

	p = (unsigned int *)addr;
	pv = (unsigned int)p;
	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
		*p++ = pv;

	p = (unsigned int *)addr;
	for (i = 0; i < size / sizeof(unsigned int); i++) {
		v = (unsigned int)p;
		vv = *p;
		if (vv != v) {
			printf("%p: read %08x instead of %08x\n", p, vv, v);
			hang();
		}
		p++;
	}

	for (j = 0; j < 5; j++) {
		switch (j) {
			case 0: v = 0x00000000; break;
			case 1: v = 0xffffffff; break;
			case 2: v = 0x55555555; break;
			case 3: v = 0xaaaaaaaa; break;
			default:v = 0xdeadbeef; break;
		}
		p = (unsigned int *)addr;
		for (i = 0; i < size / sizeof(unsigned int); i++) {
			*p = v;
			vv = *p;
			if (vv != v) {
				printf("%p: read %08x instead of %08x\n", p, vv, v);
				hang();
			}
			*p = ~v;
			p++;
		}
	}
}

#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)

long int initdram(int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size;
	u32 d1, d2;

	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));

	/*
	 * Preliminary prescaler for refresh
	 */
	memctl->memc_mptpr = MPTPR_PTP_DIV8;

	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */

	/*
	 * Map controller bank 3 to the SDRAM bank at preliminary address.
	 */
	memctl->memc_or4 = CFG_OR4_PRELIM;
	memctl->memc_br4 = CFG_BR4_PRELIM;

	memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */

	udelay(200);

	/* perform SDRAM initialisation sequence */
	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
	udelay(1);

	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
	udelay(1);

	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
	udelay(1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay(10000);


	d1 = 0xAA55AA55;
	*(volatile u32 *)0 = d1;
	d2 = *(volatile u32 *)0;
	if (d1 != d2) {
		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
		DO_LOOP;
	}

	d1 = 0x55AA55AA;
	*(volatile u32 *)0 = d1;
	d2 = *(volatile u32 *)0;
	if (d1 != d2) {
		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
		DO_LOOP;
	}

	d1 = 0x12345678;
	*(volatile u32 *)0 = d1;
	d2 = *(volatile u32 *)0;
	if (d1 != d2) {
		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
		DO_LOOP;
	}

	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);

	return size;
}

/* ------------------------------------------------------------------------- */

void reset_phys(void)
{
	int phyno;
	unsigned short v;

	udelay(10000);
	/* reset the damn phys */
	mii_init();

	for (phyno = 0; phyno < 32; ++phyno) {
		miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
		if (v == 0xFFFF)
			continue;
		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
		udelay(10000);
		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
		udelay(10000);
	}
}

/* ------------------------------------------------------------------------- */

/* GP = general purpose, SP = special purpose (on chip peripheral) */

/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_GP_INMASK	_BW(6)
#define PA_GP_OUTMASK	(_BW(7))
#define PA_SP_MASK	0
#define PA_ODR_VAL	0
#define PA_GP_OUTVAL	(_BW(7))
#define PA_SP_DIRVAL	0

#define PB_GP_INMASK	0
#define PB_GP_OUTMASK	(_B(23))
#define PB_SP_MASK	0
#define PB_ODR_VAL	0
#define PB_GP_OUTVAL	(_B(23))
#define PB_SP_DIRVAL	0

#define PC_GP_INMASK	0
#define PC_GP_OUTMASK	(_BW(15))

#define PC_SP_MASK	0
#define PC_SOVAL	0
#define PC_INTVAL	0
#define PC_GP_OUTVAL	0
#define PC_SP_DIRVAL	0

#define PE_GP_INMASK	0
#define PE_GP_OUTMASK	0
#define PE_GP_OUTVAL	0

#define PE_SP_MASK	0
#define PE_ODR_VAL	0
#define PE_SP_DIRVAL	0

int board_early_init_f(void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile iop8xx_t *ioport = &immap->im_ioport;
	volatile cpm8xx_t *cpm = &immap->im_cpm;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	(void)ioport;
	(void)cpm;
#if 1
	/* NAND chip select */
	upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
	memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
	memctl->memc_mbmr = 0;	/* all clear */
#endif

	memctl->memc_br5 &= ~BR_V;
	memctl->memc_br6 &= ~BR_V;
	memctl->memc_br7 &= ~BR_V;

#if 1
	ioport->iop_padat	= PA_GP_OUTVAL;
	ioport->iop_paodr	= PA_ODR_VAL;
	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
	ioport->iop_papar	= PA_SP_MASK;

	cpm->cp_pbdat		= PB_GP_OUTVAL;
	cpm->cp_pbodr		= PB_ODR_VAL;
	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
	cpm->cp_pbpar		= PB_SP_MASK;

	ioport->iop_pcdat	= PC_GP_OUTVAL;
	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
	ioport->iop_pcso	= PC_SOVAL;
	ioport->iop_pcint	= PC_INTVAL;
	ioport->iop_pcpar	= PC_SP_MASK;

	cpm->cp_pedat		= PE_GP_OUTVAL;
	cpm->cp_peodr		= PE_ODR_VAL;
	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
	cpm->cp_pepar		= PE_SP_MASK;
#endif

	return 0;
}

#if (CONFIG_COMMANDS & CFG_CMD_NAND)

#include <linux/mtd/nand_legacy.h>

extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

void nand_init(void)
{
	unsigned long totlen;

	totlen = nand_probe(CFG_NAND_BASE);
	printf ("%4lu MB\n", totlen >> 20);
}
#endif

#ifdef CONFIG_HW_WATCHDOG

void hw_watchdog_reset(void)
{
	/* XXX add here the really funky stuff */
}

#endif

#ifdef CONFIG_SHOW_ACTIVITY

/* called from timer interrupt every 1/CFG_HZ sec */
void board_show_activity(ulong timestamp)
{
}

/* called when looping */
void show_activity(int arg)
{
}

#endif

#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
	/* printf("overwrite_console called\n"); */
	return 0;
}
#endif

extern int drv_phone_init(void);
extern int drv_phone_use_me(void);
extern int drv_phone_is_idle(void);

int misc_init_r(void)
{
	return 0;
}

int last_stage_init(void)
{
	reset_phys();

	return 0;
}