omap2430sdp.c

OMAP2530 uboot source code

/*
 * (C) Copyright 2004-2005
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/mem.h>
#include <i2c.h>
#include <asm/mach-types.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif

void wait_for_command_complete(unsigned int wd_base);

/*******************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 ******************************************************/
static inline void delay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
			  "bne 1b":"=r" (loops):"0"(loops));
}

/*****************************************
 * Routine: board_init
 * Description: Early hardware init.
 *****************************************/
int board_init(void)
{
	u32 rev ;
	DECLARE_GLOBAL_DATA_PTR;

	gpmc_init();		/* in SRAM or SDRM, finish GPMC */
	rev = get_board_type();
	if ((rev == BOARD_H4_SDP)) {
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;	/* board id for linux */
	} else {
		gd->bd->bi_arch_number = MACH_TYPE_OMAP_2430SDP;	/* board id for linux */
	}
	gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100);	/* adress of boot parameters */

	return 0;
}

/*****************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access 
 * (GP Device only)
 *****************************************/
void secure_unlock(void)
{
	/* Permission values for registers -Full fledged permissions to all */
	#define UNLOCK_1 0xFFFFFFFF
	#define UNLOCK_2 0x00000000
	#define UNLOCK_3 0x0000FFFF
	/* Protection Module Register Target APE (PM_RT)*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50);  /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58);  /* WRITE_PERMISSION_0 L*/
	__raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/


	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/

	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
	__raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80);  /* ADDR_MATCH_2 L*/

	/* IVA Changes */
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
}

/**********************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP type, unlock the SRAM for
 *  general use.
 ***********************************************************/
void try_unlock_sram(void)
{
	int mode;

	/* if GP device unlock device SRAM for general use */
	/* secure code breaks for Secure/Emulation device - HS/E/T*/
	mode = get_device_type();
	if (mode == GP_DEVICE) {
		secure_unlock();
	}
	return;
}

/**********************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 * - Called path is with sram stack.
 **********************************************************/
void s_init(void)
{
	int in_sdram = running_in_sdram();
	/* u32 rev = get_cpu_rev(); unused as of now.. */

	watchdog_init();

	try_unlock_sram();	/* Do SRAM availability first - take care of permissions too */

	set_muxconf_regs();
	delay(100);

	if (!in_sdram){
		prcm_init();
	}

	peripheral_enable();
	icache_enable();
	if (!in_sdram)
		sdrc_init();
	
}

/*******************************************************
 * Routine: misc_init_r
 * Description: Init ethernet (done here so udelay works)
 ********************************************************/
int misc_init_r(void)
{
	ether_init();	/* better done here so timers are init'ed */
	return (0);
}

/****************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************/
void watchdog_init(void)
{
	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
	 * The ROM takes care of the secure one. Of the 3 GP ones,
	 * 1 can reset us directly, the other 2 only generate MPU interrupts.
	 */
	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
	wait_for_command_complete(WD2_BASE);
	__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
}

/******************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 ******************************************************/
void wait_for_command_complete(unsigned int wd_base)
{
	int pending = 1;
	do {
		pending = __raw_readl(wd_base + WWPS);
	} while (pending);
}

/*******************************************************************
 * Routine:ether_init
 * Description: take the Ethernet controller out of reset and wait
 *  		   for the EEPROM load to complete.
 ******************************************************************/
void ether_init(void)
{
#ifdef CONFIG_DRIVER_LAN91C96
	int cnt = 20;

	/* u32 rev = get_cpu_rev(); unused as of now */


	__raw_writew(0x0, LAN_RESET_REGISTER);
	do {
		__raw_writew(0x1, LAN_RESET_REGISTER);

		/* SSP */
		//udelay(100);
		sdelay(100);

		if (cnt == 0)
			goto h4reset_err_out;
		--cnt;
	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);

	cnt = 20;

	do {
		__raw_writew(0x0, LAN_RESET_REGISTER);
		
		/* SSP */
		//udelay(100);
		sdelay(100);

		if (cnt == 0)
			goto h4reset_err_out;
		--cnt;
	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
	
	/* SSP */
	//udelay(1000);
	sdelay(1000);

	*((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;

	/* SSP */
	//udelay(1000);
	sdelay(1000);

      h4reset_err_out:
	return;
#endif
}

/**********************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 **********************************************/
int dram_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int size0 = 0, size1 = 0;
	u32 mtype, btype;
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
	u8 data;
#endif
#define NOT_EARLY 0

#ifdef CONFIG_DRIVER_OMAP24XX_I2C
	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
	select_bus(1, CFG_I2C_SPEED);	/* select bus with T2 on it */
#endif
	btype = get_board_type();
	mtype = get_mem_type();
	display_board_info(btype);

#ifdef CONFIG_DRIVER_OMAP24XX_I2C
	if (btype == BOARD_SDP_2430_T2) {		
		/* Enable VMODE following voltage switching */
		data = 0x24;  /* set the floor voltage to 1.05v */
		i2c_write(I2C_TRITON2, 0xBB, 1, &data, 1);   
		data = 0x38; /* set the roof voltage to 1.3V */
		i2c_write(I2C_TRITON2, 0xBC, 1, &data, 1);		
		data = 0x0; /* set jump mode for VDD voltage transition */
		i2c_write(I2C_TRITON2, 0xBD, 1, &data, 1);  
		data = 1; /* enable voltage scaling */
		i2c_write(I2C_TRITON2, 0xBA, 1, &data, 1); 
	}
#endif

	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
		/* init other chip select and map CS1 right after CS0 */
		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
	}
	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
	size1 = get_sdr_cs_size(SDRC_CS1_OSET);

	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = size0;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
	gd->bd->bi_dram[1].size = size1;

	return 0;
}

#define MUX_VAL(OFFSET,VALUE)\
		__raw_writeb((VALUE), OMAP24XX_CTRL_BASE + (OFFSET));

#if (CONFIG_2430SDP)
#define MUX_DEFAULT()\
	/* SDRC */\
	MUX_VAL(0x0054, 0x1B)		/* sdrc_a14 - EN, HI, 3, ->gpio_0 */\
	MUX_VAL(0x0055, 0x1B)		/* sdrc_a13 - EN, HI, 3, ->gpio_1 */\
	MUX_VAL(0x0056, 0x00)		/* sdrc_a12 - Dis, 0 */\
	MUX_VAL(0x0046, 0x00)		/* sdrc_ncs1 - Dis, 0 */\
	MUX_VAL(0x0048, 0x00)		/* sdrc_cke1 - Dis, 0 */\
	/* GPMC */\
	MUX_VAL(0x0030, 0x00)		/* gpmc_clk - Dis, 0 */\
	MUX_VAL(0x0032, 0x00)		/* gpmc_ncs1- Dis, 0 */\
	MUX_VAL(0x0033, 0x00)		/* gpmc_ncs2- Dis, 0 */\
	MUX_VAL(0x0034, 0x03)		/* gpmc_ncs3- Dis, 3, ->gpio_24 */\
	MUX_VAL(0x0035, 0x03)		/* gpmc_ncs4- Dis, 3, ->gpio_25 */\
	MUX_VAL(0x0036, 0x00)		/* gpmc_ncs5- Dis, 0 */\
	MUX_VAL(0x0037, 0x03)		/* gpmc_ncs6- Dis, 3, ->gpio_27 */\
	MUX_VAL(0x0038, 0x00)		/* gpmc_ncs7- Dis, 0 */\
	MUX_VAL(0x0040, 0x18)		/* gpmc_wait1- Dis, 0 */\
	MUX_VAL(0x0041, 0x18)		/* gpmc_wait2- Dis, 0 */\
	MUX_VAL(0x0042, 0x1B)		/* gpmc_wait3- EN, HI, 3, ->gpio_35 */\
	MUX_VAL(0x0085, 0x1B)		/* gpmc_a10- EN, HI, 3, ->gpio_3 */\
	/* GPMC mux for NAND access */\
        MUX_VAL(0x0086, 0x18)		/* gpmc_a9 - EN, HI, 0*/\
        MUX_VAL(0x0087, 0x18)		/* gpmc_a8 - EN, HI, 0*/\