mem.c

OMAP2530 uboot source code

void sdrc_init(void)
{
#define EARLY_INIT 1
	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);	/* only init up first bank here */
}

/*************************************************************************
 * do_sdrc_init(): initialize the SDRAM for use.
 *  -called from low level code with stack only.
 *  -code sets up SDRAM timing and muxing for 2422 or 2420.
 *  -optimal settings can be placed here, or redone after i2c
 *      inspection of board info
 *
 *  This is a bit ugly, but should handle all memory modules
 *   used with the SDP. The first time though this code from s_init()
 *   we configure the first chip select.  Later on we come back and
 *   will configure the 2nd chip select if it exists.
 *
 **************************************************************************/
void do_sdrc_init(u32 offset, u32 early)
{
	u32 cpu, dev, dllstat, dllctrl = 0, rev, common = 0, cs0 = 0, pmask =
	    0, pass_type, mtype;
	sdrc_data_t *sdata;	/* do not change type */
	u32 dllx = 0, mono = 0;
	void init_dcdl(u32 cpu);

	/* the following structure has a lot data shared with 2420 H4. Only 3 2430SDP
	   parameters. This needs to be cleaned after wakeup */
	static const sdrc_data_t sdrc_2430 = {
		H4_2420_SDRC_SHARING, SDP_2430_SDRC_MDCFG_0_DDR,
		H4_2420_SDRC_MDCFG_0_SDR,
		SDP_2430_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR,
		H4_2420_SDRC_MR_0_SDR,
		SDP_2430_SDRC_DLLAB_CTRL
	};

	if (offset == SDRC_CS0_OSET)
		cs0 = common = 1;	/* int regs shared between both chip select */

	cpu = get_cpu_type();
	dev = get_device_type();
	rev = get_cpu_rev();

	/* warning generated, though code generation is correct. this may bite later,
	 * but is ok for now. there is only so much C code you can do on stack only
	 * operation.
	 */
	sdata = (sdrc_data_t *) & sdrc_2430;
	pass_type = IP_DDR;

	__asm__ __volatile__("":::"memory");	/* limit compiler scope */

	/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
	 * If we are running in flash prior to relocation and we use data
	 * here which is not pc relative we need to get the address correct.
	 * We need to find the current flash mapping to dress up the initial
	 * pointer load.  As long as this is const data we should be ok.
	 */
	if ((early) && running_in_flash()) {
		sdata =
		    (sdrc_data_t *) (((u32) sdata & 0x0003FFFF) |
				     get_gpmc0_base());
		if (running_from_internal_boot()) {
			if (dev != GP_DEVICE)
				/* NOR internal boot for HS device offset is 
				 * 0x4000 from xloader signature.
				 */
				sdata = (sdrc_data_t *) ((u32) sdata + 0x4000);
			else {
				/* GP device, the image may or may not signed.
				 * If signed, there are 8 bytes pending so the
				 * u-boot is at offset 0x8.
				 */
				if (sdata->sdrc_sharing != H4_2420_SDRC_SHARING)
					sdata =
					    (sdrc_data_t *) ((u32) sdata + 0x8);
			}
		}
	}

	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)
		       || (mtype == DDR_STACKED))) {
		if (mtype == DDR_COMBO) {
			pmask = BIT2;	/* combo part has a shared CKE signal, can't use feature */
			pass_type = COMBO_DDR;	/* CS1 config */
			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask,
				     SDRC_POWER);
		}
		if (rev != CPU_242X_ES1)	/* for es2 and above smooth things out */
			make_cs1_contiguous();
	}

      next_mem_type:
	if (common) {		/* do a SDRC reset between types to clear regs */
		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);	/* wait till reset done set */
		__raw_writel(0, SDRC_SYSCONFIG);	/* clear soft reset */
		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
#ifdef POWER_SAVE
		__raw_writel(__raw_readl(SMS_SYSCONFIG) | SMART_IDLE,
			     SMS_SYSCONFIG);
		__raw_writel(sdata->sdrc_sharing | SMART_IDLE, SDRC_SHARING);
		__raw_writel((__raw_readl(SDRC_POWER) | BIT6), SDRC_POWER);
#endif
	}

	if ((pass_type == IP_DDR) || (pass_type == STACKED)) {	/* (IP ddr-CS0),(2422-CS0/CS1) */
		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0 + offset);
		if (mono)
			__raw_writel(H4_2422_SDRC_MDCFG_MONO_DDR, SDRC_MCFG_0 + offset);	/* 2422.es2.05-CS1 */
	} else if (pass_type == COMBO_DDR) {	/* (combo-CS0/CS1) */
		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0 + offset);
	} else if (pass_type == IP_SDR) {	/* ip sdr-CS0 */
		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0 + offset);
	}

	if (cs0) {
		__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_0);
		__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_0);
	} else {
		__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_1);
		__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_1);
	}
	__raw_writel(sdata->sdrc_rfr_ctrl, SDRC_RFR_CTRL + offset);

	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
	__raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset);
	sdelay(5000);		/* supposed to be 100us per design spec for mddr/msdr */
	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset);

	/*
	 * CSx SDRC Mode Register
	 * Burst length = (4 - DDR) (2-SDR)
	 * Serial mode
	 * CAS latency = x
	 */
	if (pass_type == IP_SDR)
		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0 + offset);
	else
		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0 + offset);

	dllctrl = BIT0; /* flag to clear bit0 (90deg for < 133MHz) */

#ifdef PRCM_CONFIG_2
	/* flag clear bit1 (set phase to 72 for > 150MHz) */
	dllctrl |= DLLPHASE;	/* phase to 72 for > 150MHz) */
#endif

	/* If DDR enable DLL to get a value, then move to unlock mode for SDRC mod16 errata */
	if (common && (pass_type != IP_SDR)) {
		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
		__raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL | dllctrl),
			     SDRC_DLLA_CTRL);
		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
		__raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL | dllctrl),
			     SDRC_DLLB_CTRL);

		init_dcdl(cpu);	/* fix errata for possible bad init state */

		sdelay(0x2000);	/* give time to lock, at least 1000 L3 */

		/* work around DCDL MOD16 bug */
		dllctrl = __raw_readl(SDRC_DLLA_CTRL + dllx);	/* get cur ctrl value */
		dllctrl &= ~(DLL_DELAY_MASK);	/* prepare for load new value */
		dllctrl |= LOADDLL;	/* prepare for load + unlock mode */
		dllstat =
		    (__raw_readl(SDRC_DLLA_STATUS + dllx) & DLL_DELAY_MASK);
		dllctrl |= dllstat;	/* prepare new dll load delay */
		dllctrl |= DLL_NO_FILTER_MASK;	/* make sure filter is off */
		__raw_writel(dllctrl, SDRC_DLLA_CTRL);	/* go to unlock modeA */
		__raw_writel(dllctrl, SDRC_DLLB_CTRL);	/* go to unlock modeB */
	}
	sdelay(0x1000);

	if (mono)		/* Used if Stacked memory is on CS1 only */
		make_cs1_contiguous();	/* make CS1 appear at CS0 */

	if (mem_ok())
		return;		/* STACKED, other configured type */
	++pass_type;		/* IPDDR->COMBODDR->IPSDR for CS0 */
	goto next_mem_type;
}

/*****************************************************
 * init_dcdl(): Fix errata - unitilized flip-flop.
 *****************************************************/
void init_dcdl(u32 cpu)
{
	volatile u8 *adqs[4];
	u8 vdqs[4], idx, i;
	u32 base = OMAP24XX_CTRL_BASE;
#define CONTROL_SDRC_DQS0 0x50

	adqs[0] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x0));
	adqs[1] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x1));
	adqs[2] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x2));
	adqs[3] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x3));
	idx = 4;

	for (i = 0; i < idx; ++i)	/* save origional state */
		vdqs[i] = *adqs[i];

	for (i = 0; i < idx; ++i)
		*adqs[i] = ((~0x10 & vdqs[i]) | 0x8);	/* enable/activate pull down */

	sdelay(0x400);

	for (i = 0; i < idx; ++i)
		*adqs[i] = (vdqs[i] | 0x10);	/* enable/activate pull up */

	sdelay(0x400);

	for (i = 0; i < idx; ++i)	/* restore state */
		*adqs[i] = vdqs[i];
}

void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size)
{
	__raw_writel(0, GPMC_CONFIG7 + gpmc_base);
	sdelay(1000);
	/* Delay for settling */
	__raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base);
	__raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base);
	__raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base);
	__raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base);
	__raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base);
	__raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base);
	/* Enable the config */
	__raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
		      (1 << 6)), GPMC_CONFIG7 + gpmc_base);
	sdelay(2000);
}

/*****************************************************
 * gpmc_init(): init gpmc bus
 * Init GPMC for x16, MuxMode (SDRAM in x32).
 * This code can only be executed from SRAM or SDRAM.
 *****************************************************/
void gpmc_init(void)
{
	/* For readability */
	u32 mux = 0, mwidth;
	u32 *gpmc_config = NULL;
	u32 gpmc_base = 0;
	u32 base = 0;
	u8 idx = 0;
	u8 cnt = 0;
	u32 size = 0;
	u32 f_off = CFG_MONITOR_LEN;
	u32 f_sec = 0;
	u32 board_type = 0;
	unsigned char *config_sel = NULL;

	mux = BIT9;
	mwidth = get_gpmc0_width();

	/* global settings */
	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
	__raw_writel(0, GPMC_TIMEOUT_CONTROL);	/* timeout disable */

	/* Disable the GPMC0 config set by ROM code
	 * It conflicts with our MPDB (both at 0x08000000)
	 */
	__raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
	sdelay(1000);

	/* GPMC5 is always MPDB.. need to know the chip info */
	gpmc_base = GPMC_CONFIG_CS0 + (5 * GPMC_CONFIG_WIDTH);
	gpmc_mpdb[0] |= mux;
	enable_gpmc_config(gpmc_mpdb, gpmc_base, DEBUG_BASE, DBG_MPDB_SIZE);
	idx = get_gpmc0_type();
	/* invalid chip, assume nor boot */
	if (idx > 0x7) {
		idx = 7;
	}
	board_type = get_sdp_type();

	if (board_type == BOARD_GDP_2430_T2) {

		config_sel = (unsigned char *)(chip_sel_gdp[idx]);

		/* GPMC7 is always PCMCIA.. need to know the chip info */
		gpmc_base = GPMC_CONFIG_CS0 + (7 * GPMC_CONFIG_WIDTH);
		gpmc_pcmcia[0] |= mux;
		__raw_writel(0x0, GPMC_CONFIG);	/* set nWP, disable limited addr */
		enable_gpmc_config(gpmc_pcmcia, gpmc_base, PCMCIA_BASE,PISMO_PCMCIA_SIZE );

		/* On GDP, all the 4 flashes are not present by default 
		 * Configure only those flashes that are present.
		 */
		NOR_MAX_FLASH_BANKS = norfl_loc_gdp[idx][0];
		
		for (cnt = 1; cnt <= NOR_MAX_FLASH_BANKS ; cnt++) {
			NOR_FLASH_BANKS_LIST[cnt - 1] = norfl_loc_gdp[idx][cnt];
		}
		
	} else {
		config_sel = (unsigned char *)(chip_sel_sdp[idx]);
	}

	/* For Nand based boot only..OneNand?? */
	if (config_sel[0] == PROC_NAND) {
		__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
	}
	/* reuse idx */
	for (idx = 0; idx < GPMC_MAX_CS; idx++) {
		if (!config_sel[idx]) {
			continue;
		}
		gpmc_base = GPMC_CONFIG_CS0 + (idx * GPMC_CONFIG_WIDTH);
		switch (config_sel[idx]) {
		case PROC_NOR:
			gpmc_config = gpmc_stnor;
			gpmc_config[0] |= mux | TYPE_NOR | mwidth;
			base = PROC_NOR_BASE;
			size = PROC_NOR_SIZE;
			f_sec = SZ_128K;
			is_flash = 1;
			break;
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
		case PROC_NAND:
			base = PROC_NAND_BASE;
			size = PROC_NAND_SIZE;
			gpmc_config = gpmc_smnand;
			gpmc_config[0] |= mux | TYPE_NAND | mwidth;
			/* Either OneNand or Normal Nand at a time!! */
			nand_cs_base = gpmc_base;
			f_off = SMNAND_ENV_OFFSET;
			is_nand = 1;
			break;
#endif
		case PISMO_SIBLEY0:
		case PISMO_SIBLEY1:
			if (config_sel[idx] == PISMO_SIBLEY0) {
				base = PISMO_SIB0_BASE;
				size = PISMO_SIB0_SIZE;
			} else {
				base = PISMO_SIB1_BASE;
				size = PISMO_SIB1_SIZE;
			}
			f_sec = SZ_256K;
			gpmc_config = gpmc_sibnor;
			gpmc_config[0] |= mux | TYPE_NOR | mwidth;
			is_flash = 1;
			break;
/* SSP - protect it */
#if		( (!CFG_NAND_BOOT) & (CONFIG_COMMANDS & CFG_CMD_ONENAND ) )
		case PISMO_ONENAND:
			base = PISMO_ONEN_BASE;
			size = PISMO_ONEN_SIZE;
			gpmc_config = gpmc_onenand;
			f_off = ONENAND_ENV_OFFSET;
			is_onenand = 1;
			break;
#endif
		default:
			/* MPDB/Unsupported/Corrupt config- try Next GPMC CS!!!! */
			continue;
		}
		if (0 == idx) {
			boot_flash_base = base;
			boot_flash_off = f_off;
			boot_flash_sec = f_sec;
			boot_flash_type = config_sel[idx];
			boot_flash_env_addr = f_off;
#ifdef ENV_IS_VARIABLE
			switch (config_sel[0]) {
			case PROC_NOR:
			case PISMO_SIBLEY0:
			case PISMO_SIBLEY1:
				boot_env_get_char_spec =
				    flash_env_get_char_spec;
				boot_env_init = flash_env_init;
				boot_saveenv = flash_saveenv;
				boot_env_relocate_spec =
				    flash_env_relocate_spec;
				flash_addr = env_ptr =
				    (env_t *) (boot_flash_base +
					       boot_flash_off);
				env_name_spec = flash_env_name_spec;
				boot_flash_env_addr = (u32) flash_addr;
				break;
#ifdef CFG_NAND_BOOT
			case PROC_NAND:
				boot_env_get_char_spec = nand_env_get_char_spec;
				boot_env_init = nand_env_init;
				boot_saveenv = nand_saveenv;
				boot_env_relocate_spec = nand_env_relocate_spec;

//				env_ptr = 0;	/* This gets filled elsewhere!! */
//				env_name_spec = nand_env_name_spec;

				break;
#endif

/* SSP - protect */
#if     ( (!CFG_NAND_BOOT) & CFG_ENV_IS_IN_ONENAND )
			case PISMO_ONENAND:
				boot_env_get_char_spec =
				    onenand_env_get_char_spec;
				boot_env_init = onenand_env_init;
				boot_saveenv = onenand_saveenv;
				boot_env_relocate_spec =
				    onenand_env_relocate_spec;
				env_ptr =
				    (env_t *) onenand_env;
				env_name_spec = onenand_env_name_spec;
				break;
#endif
			default:
				/* unknown variant!! */
				puts("Unknown Boot chip!!!\n");
				break;
			}
#endif				/* ENV_IS_VARIABLE */
		}
		enable_gpmc_config(gpmc_config, gpmc_base, base, size);
	}
}