mem.c

OMAP2530 uboot source code

/*
 * (C) Copyright 2004-2005
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <environment.h>
#include <command.h>

/****** DATA STRUCTURES ************/

/* Only One NAND allowed on board at a time. 
 * The GPMC CS Base for the same
 */
unsigned int nand_cs_base = 0;
unsigned int boot_flash_base = 0;
unsigned int boot_flash_off = 0;
unsigned int boot_flash_sec = 0;
unsigned int boot_flash_type = 0;
volatile unsigned int boot_flash_env_addr = 0;
/* help common/env_flash.c */
#ifdef ENV_IS_VARIABLE

/* On SDP, all the 3 NOR parts are available on all CS combinations.
 * On GDP, this is a variable set. Set the default to SDP configuration
 * and change it later on if the board is GDP.
 */
ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
int NOR_MAX_FLASH_BANKS = 4 ;           /* max number of flash banks */

uchar(*boot_env_get_char_spec) (int index);
int (*boot_env_init) (void);
int (*boot_saveenv) (void);
void (*boot_env_relocate_spec) (void);

extern uchar flash_env_get_char_spec(int index);
extern int flash_env_init(void);
extern int flash_saveenv(void);
extern void flash_env_relocate_spec(void);
extern char *flash_env_name_spec;

extern uchar nand_env_get_char_spec(int index);
extern int nand_env_init(void);
extern int nand_saveenv(void);
extern void nand_env_relocate_spec(void);
extern char *nand_env_name_spec;

extern char *onenand_env;
extern uchar onenand_env_get_char_spec(int index);
extern int onenand_env_init(void);
extern int onenand_saveenv(void);
extern void onenand_env_relocate_spec(void);
extern char *onenand_env_name_spec;

/* Global fellows */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
u8 is_nand = 0;
#endif

#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
u8 is_flash = 0;
#endif

#if (CONFIG_COMMANDS & CFG_CMD_ONENAND)
u8 is_onenand = 0;
#endif

#ifdef CFG_NAND_BOOT
extern char * env_name_spec;
extern env_t * env_ptr;
#else
char *env_name_spec = 0;
/* update these elsewhere */
env_t *env_ptr = 0;
#endif


#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
extern env_t *flash_addr;
#endif

#endif				/* ENV_IS_VARIABLE */

/* Board CS Organization - 2430SDP REV 0.1->1.1 */
static const unsigned char chip_sel_sdp[][GPMC_MAX_CS] = {
/* GPMC CS Indices */
/* S8- 1   2   3 IDX    CS0,       CS1,      CS2 ..                          CS7  */
/* 0 OFF OFF OFF */ {PISMO_CS2, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_CS0},
/* 1 ON  OFF OFF */ {PISMO_CS1, PISMO_CS0, PROC_NOR, 0, 0, DBG_MPDB, 0, PROC_NAND},
/* 2 OFF ON  OFF */ {PISMO_CS0, PROC_NOR, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_CS2},
/* 3 ON  ON  OFF */ {PROC_NAND, PROC_NOR, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1},
/* 4 OFF OFF ON  */ {PISMO_CS1, PISMO_CS2, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_CS0},
/* 5 ON  OFF ON  */ {PISMO_CS0, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PROC_NAND},
/* 6 OFF ON  ON  */ {PROC_NOR, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_CS2},
/* 7 ON  ON  ON  */ {PROC_NOR, PROC_NAND, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1},
};

/* Board CS Organization - 2430GDP REV 0.1->1.1 */
static const unsigned char chip_sel_gdp[][GPMC_MAX_CS] = {
/* GPMC CS Indices */
/* S8- 1   2   3 IDX    CS0,       CS1,      CS2 ..                          CS7  */
/* 0 OFF OFF OFF */ {PISMO_CS0, PISMO_CS1, PROC_NAND, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 1 ON  OFF OFF */ {PISMO_CS2, PROC_NAND, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 2 OFF ON  OFF */ {PROC_NAND, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 3 ON  ON  OFF */ {PROC_NAND, PROC_NOR, PISMO_CS2, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 4 OFF OFF ON  */ {PISMO_CS0, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 5 ON  OFF ON  */ {PISMO_CS2, PROC_NOR, PROC_NAND, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 6 OFF ON  ON  */ {PROC_NOR, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
/* 7 ON  ON  ON  */ {PROC_NOR, PROC_NAND, PISMO_CS2, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA},
};

/* Map the number of NORs present and NOR flash locations on GDP */
static const ulong norfl_loc_gdp[][CFG_MAX_FLASH_BANKS + 1] = {
/* 0 OFF OFF OFF*/ {2,SIBLEY_MAP1, SIBLEY_MAP2, 0, 0 },
/* 1 ON  OFF OFF*/ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0},
/* 2 OFF ON  OFF*/ {2,SIBLEY_MAP1, SIBLEY_MAP2, 0, 0 }, 
/* 3 ON  ON  OFF*/ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, 
/* 4 OFF OFF ON */ {4,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, SIBLEY_MAP1, SIBLEY_MAP2}, 
/* 5 ON  OFF ON */ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, 
/* 6 OFF ON  ON */ {4, FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, SIBLEY_MAP1, SIBLEY_MAP2},
/* 7 ON  ON  ON */ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0},
};
/* Values for each of the chips */
static u32 gpmc_mpdb[GPMC_MAX_REG] = {
	MPDB_GPMC_CONFIG1,
	MPDB_GPMC_CONFIG2,
	MPDB_GPMC_CONFIG3,
	MPDB_GPMC_CONFIG4,
	MPDB_GPMC_CONFIG5,
	MPDB_GPMC_CONFIG6, 0
};
static u32 gpmc_stnor[GPMC_MAX_REG] = {
	STNOR_GPMC_CONFIG1,
	STNOR_GPMC_CONFIG2,
	STNOR_GPMC_CONFIG3,
	STNOR_GPMC_CONFIG4,
	STNOR_GPMC_CONFIG5,
	STNOR_GPMC_CONFIG6, 0
};
static u32 gpmc_smnand[GPMC_MAX_REG] = {
	SMNAND_GPMC_CONFIG1,
	SMNAND_GPMC_CONFIG2,
	SMNAND_GPMC_CONFIG3,
	SMNAND_GPMC_CONFIG4,
	SMNAND_GPMC_CONFIG5,
	SMNAND_GPMC_CONFIG6, 0
};
static u32 gpmc_sibnor[GPMC_MAX_REG] = {
	SIBNOR_GPMC_CONFIG1,
	SIBNOR_GPMC_CONFIG2,
	SIBNOR_GPMC_CONFIG3,
	SIBNOR_GPMC_CONFIG4,
	SIBNOR_GPMC_CONFIG5,
	SIBNOR_GPMC_CONFIG6, 0
};
static u32 gpmc_onenand[GPMC_MAX_REG] = {
	ONENAND_GPMC_CONFIG1,
	ONENAND_GPMC_CONFIG2,
	ONENAND_GPMC_CONFIG3,
	ONENAND_GPMC_CONFIG4,
	ONENAND_GPMC_CONFIG5,
	ONENAND_GPMC_CONFIG6, 0
};
static u32 gpmc_pcmcia[GPMC_MAX_REG] = {
	PCMCIA_GPMC_CONFIG1,
	PCMCIA_GPMC_CONFIG2,
	PCMCIA_GPMC_CONFIG3,
	PCMCIA_GPMC_CONFIG4,
	PCMCIA_GPMC_CONFIG5,
	PCMCIA_GPMC_CONFIG6, 0
};

/********** Functions ****/

/* ENV Functions */

#ifdef ENV_IS_VARIABLE
uchar env_get_char_spec(int index)
{
	if (!boot_env_get_char_spec) {
		puts("ERROR!! env_get_char_spec not available\n");
	} else
		return boot_env_get_char_spec(index);
	return 0;
}
int env_init(void)
{
	if (!boot_env_init) {
		puts("ERROR!! boot_env_init not available\n");
	} else
		return boot_env_init();
	return -1;
}
int saveenv(void)
{
	if (!boot_saveenv) {
		puts("ERROR!! boot_saveenv not available\n");
	} else
		return boot_saveenv();
	return -1;
}
void env_relocate_spec(void)
{
	if (!boot_env_relocate_spec) {
		puts("ERROR!! boot_env_relocate_spec not available\n");
	} else
		boot_env_relocate_spec();
}
#endif

/*************************************************************
 * get_sys_clk_speed - determine reference oscillator speed
 *  based on known 32kHz clock and gptimer.
 *************************************************************/
u32 get_osc_clk_speed(u32 * shift)
{
#define GPT_EN	((0<<2)|BIT1|BIT0)	/* enable sys_clk NO-prescale /1 */
#define GPT_CTR	OMAP24XX_GPT2+TCRR	/* read counter address */
	u32 start, cstart, cend, cdiff, val;

	if (__raw_readl(PRCM_CLKSRC_CTRL) & BIT7) {	/* if currently /2 */
		*shift = 1;
	} else {
		*shift = 0;
	}

	/* enable timer2 */
	val = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* mask for sys_clk use */
	__raw_writel(val, CM_CLKSEL2_CORE);	/* timer2 source to sys_clk */
	__raw_writel(BIT4, CM_ICLKEN1_CORE);	/* timer2 interface clock on */
	__raw_writel(BIT4, CM_FCLKEN1_CORE);	/* timer2 function clock on */
	__raw_writel(0, OMAP24XX_GPT2 + TLDR);	/* start counting at 0 */
	__raw_writel(GPT_EN, OMAP24XX_GPT2 + TCLR);	/* enable clock */
	/* enable 32kHz source *//* enabled out of reset */
	/* determine sys_clk via gauging */

	start = 20 + __raw_readl(S32K_CR);	/* start time in 20 cycles */
	while (__raw_readl(S32K_CR) < start) ;	/* dead loop till start time */
	cstart = __raw_readl(GPT_CTR);	/* get start sys_clk count */
	while (__raw_readl(S32K_CR) < (start + 20)) ;	/* wait for 40 cycles */
	cend = __raw_readl(GPT_CTR);	/* get end sys_clk count */
	cdiff = cend - cstart;	/* get elapsed ticks */

	/* based on number of ticks assign speed */
	if (cdiff > (19000 >> *shift))
		return (S38_4M);
	else if (cdiff > (15200 >> *shift))
		return (S26M);
	else if (cdiff > (13000 >> *shift))
		return (S24M);
	else if (cdiff > (9000 >> *shift))
		return (S19_2M);
	else if (cdiff > (7600 >> *shift))
		return (S13M);
	else
		return (S12M);
}

/************************************************************
 * sdelay() - simple spin loop.  Will be constant time as
 *  its generally used in 12MHz bypass conditions only.  This
 *  is necessary until timers are accessible.
 *
 *  not inline to increase chances its in cache when called
 *************************************************************/
void sdelay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
			  "bne 1b":"=r" (loops):"0"(loops));
}

/*********************************************************************************
 * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
 *   -- called from SRAM, or Flash (using temp SRAM stack).
 *********************************************************************************/
void prcm_init(void)
{
	u32 div, speed, val, div_by_2;
	void (*f_lock_pll) (u32, u32, u32, u32);
	extern void *_end_vect, *_start;
	/* u32 rev = get_cpu_rev(); unused as of now */

	f_lock_pll =
	    (void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE);

	val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0);
#if defined(OMAP2430_SQUARE_CLOCK_INPUT)
	__raw_writel(val, PRCM_CLKSRC_CTRL);
#else
	__raw_writel((val | BIT0), PRCM_CLKSRC_CTRL);
#endif
	/* skip clock gauging if warm reset. For some unknown reason,
	   GPT2 stalls after warm reset until DPLL has been setup and
	   GPT2 F/I clocks are enabled.
	 */
	if (__raw_readl(RM_RSTST_MPU) & BIT1) {
		speed = S13M;
		if (((BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL)) ==
		    (0x3 << 23))
			speed = S12M;
		else if (((BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL))
			 == (0x0 << 23))
			speed = S19_2M;
		div_by_2 =
		    (((BIT6 | BIT7) & __raw_readl(PRCM_CLKSRC_CTRL)) == 0x2);
		if (div_by_2)
			speed <<= 1;
	} else
		speed = get_osc_clk_speed(&div_by_2);

	if ((speed > S19_2M) && (!div_by_2)) {	/* if fast && /2 off, enable it */
		val = ~(BIT6 | BIT7) & __raw_readl(PRCM_CLKSRC_CTRL);
		val |= (0x2 << 6);	/* divide by 2 if (24,26,38.4) -> (12/13/19.2)  */
		__raw_writel(val, PRCM_CLKSRC_CTRL);
	}
	__raw_writel(0, CM_FCLKEN1_CORE);	/* stop all clocks to reduce ringing */
	__raw_writel(0, CM_FCLKEN2_CORE);	/* may not be necessary */
	__raw_writel(0, CM_ICLKEN1_CORE);
	__raw_writel(0, CM_ICLKEN2_CORE);

	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
	__raw_writel(MDM_DIV, CM_CLKSEL_MDM);	/* set mdm dividers */

	div = BUS_DIV;
	__raw_writel(div, CM_CLKSEL1_CORE);	/* set L3/L4/USB/Display/SSi dividers */
	sdelay(1000);

	if (running_in_flash()) {
		/* if running from flash, need to jump to small relocated code area in SRAM.
		 * This is the only safe spot to do configurations from.
		 */
		(*f_lock_pll) (PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK,
			       CM_IDLEST_CKGEN);
	}

	/* set up APLLS_CLKIN per crystal */
	if (speed > S19_2M)
		speed >>= 1;	/* if fast shift to /2 range */
	val = (0x2 << 23);	/* default to 13Mhz for 2430c */
	if (speed == S12M)
		val = (0x3 << 23);
	else if (speed == S19_2M)
		val = (0x0 << 23);
	val |= (~(BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL));
	__raw_writel(val, CM_CLKSEL1_PLL);

	__raw_writel(DPLL_LOCK | APLL_LOCK, CM_CLKEN_PLL);	/* enable apll */
	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */

	sdelay(1000);
}

/**************************************************************************
 * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
 *  command line mem=xyz use all memory with out discontigious support
 *  compiled in.  Could do it at the ATAG, but there really is two banks...
 * Called as part of 2nd phase DDR init.
 **************************************************************************/
void make_cs1_contiguous(void)
{
	u32 size, a_add_low, a_add_high;

	size = get_sdr_cs_size(SDRC_CS0_OSET);
	size /= SZ_32M;		/* find size to offset CS1 */
	a_add_high = (size & 3) << 8;	/* set up low field */
	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
	__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);

}

/********************************************************
 *  mem_ok() - test used to see if timings are correct
 *             for a part. Helps in gussing which part
 *             we are currently using.
 *******************************************************/
u32 mem_ok(void)
{
	u32 val1, val2, addr;
	u32 pattern = 0x12345678;

	addr = OMAP24XX_SDRC_CS0;

	__raw_writel(0x0, addr + 0x400);	/* clear pos A */
	__raw_writel(pattern, addr);	/* pattern to pos B */
	__raw_writel(0x0, addr + 4);	/* remove pattern off the bus */
	val1 = __raw_readl(addr + 0x400);	/* get pos A value */
	val2 = __raw_readl(addr);	/* get val2 */

	if ((val1 != 0) || (val2 != pattern))	/* see if pos A value changed */
		return (0);
	else
		return (1);
}

/********************************************************
 *  sdrc_init() - init the sdrc chip selects CS0 and CS1
 *  - early init routines, called from flash or
 *  SRAM.
 *******************************************************/