lcd_control.v

LCD的驱动显示程序,在SP3实验板上实现.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:02:35 12/08/2007 
// Design Name: 	 CMKing
// Module Name:    lcd_control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_control(clk, reset, lcd_rs, lcd_rw, lcd_e, lcd_d, stataflash_oe, stataflash_ce, stataflash_we);

    input clk;
    input reset;

    output lcd_rs;
    output lcd_rw;
    output lcd_e;

    output stataflash_oe;
    output stataflash_ce;
    output stataflash_we;

    output [3:0] lcd_d;

	 reg lcd_rs,lcd_e;
	 reg [3:0] lcd_d;
	 reg [7:0] wr_data;
	 
/*Holding all three controls High ensures that the StrataFLASH
memory does not interfere with the LCD display and also prevents
inadvertent modifications to the memory contents.	 */
	 assign stataflash_oe = 1;
	 assign stataflash_ce = 1;
	 assign stataflash_we = 1;

//In a write only system, the R/W signal can be tied Low permanently 
    assign lcd_rw = 0;

//Delay control
	 reg [19:0] delay_count;
	 reg [19:0] num_count;
	 reg [3:0]	num_cm_da;
	 reg lcd_rs_define;
	 
//State-Machine define
   parameter state1  = 18'b000000000000000001; //1
   parameter state2  = 18'b000000000000000010;	//2
   parameter state3  = 18'b000000000000000100;	//4
   parameter state4  = 18'b000000000000001000;	//8
   parameter state5  = 18'b000000000000010000;	//16
   parameter state6  = 18'b000000000000100000;	//32
   parameter state7  = 18'b000000000001000000;	//64
   parameter state8  = 18'b000000000010000000;	//128
   parameter state9  = 18'b000000000100000000;	//256
   parameter state10 = 18'b000000001000000000;
   parameter state11 = 18'b000000010000000000;
   parameter state12 = 18'b000000100000000000;
   parameter state13 = 18'b000001000000000000;
   parameter state14 = 18'b000010000000000000;
   parameter state15 = 18'b000100000000000000;
   parameter state16 = 18'b001000000000000000;
	parameter state17 = 18'b010000000000000000;
	parameter state18 = 18'b100000000000000000;
	
	reg [17:0] state;
	reg state_change;
			
	always @ (posedge clk or posedge reset)
		if (reset)
			state_change <= 1'b0;
		else
			if (delay_count == num_count - 1)
				state_change <= 1'b1;
			else
				state_change <= 1'b0;
				
	always @ (negedge state_change or posedge reset)
		if (reset)
			begin
				state <= state1;
				num_cm_da <= 4'd0;
			end
		else
			case (state)
				state1 :	state <= state2;
				state2 :	state <= state3;
				state3 : state <= state4;
				state4 : state <= state5;
				state5 : state <= state6;
				state6 : state <= state7;
				state7 : state <= state8;
				state8 : state <= state9;
				state9 : state <= state10;
				state10 : state <= state11;
				state11 : state <= state12;
				state12 : state <= state13;
				state13 : state <= state14;
				state14 : state <= state15;
				state15 : begin
								state <= state16;
							if (num_cm_da <= 4'd4)
								num_cm_da <= num_cm_da + 1'b1;
							end
				state16 : begin
					if (num_cm_da == 4'd4)
						state <= state17;
					else
//						begin
//							if (num_cm_da <= 4'd4)
//								num_cm_da <= num_cm_da + 1'b1;
							state <= state11;
//						end
					end
				state17 : begin
								state <= state11;
							//	num_cm_da <= num_cm_da + 1'b1;
							end
				default : state <= state1;
			endcase
			
	always @ (state)
			case (state)
				state1:
					begin
						num_count <= 20'd900000;//900000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h3;
					end
				state2:
					begin
						num_count <= 20'd50;//keep lcd_e high for more than 230ns//50
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b1;
						lcd_d  <= 4'h3;
					end
				state3:
					begin
						num_count <= 20'd900000;//900000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h3;
					end
				state4:
					begin
						num_count <= 20'd50;//50
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b1;
						lcd_d  <= 4'h3;
					end
				state5:
					begin
						num_count <= 20'd6000;//wait > 100us (10us for lcd_e neg edge)//6000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h3;
					end
				state6:
					begin
						num_count <= 20'd50;//50
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b1;
						lcd_d  <= 4'h3;
					end
				state7:
					begin
						num_count <= 20'd3000;//wait>40us (10ns for lcd_e neg edge)//3000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h3;
					end
				state8:
				   begin
						num_count <= 20'd10;//wait>40ns for setup time//10
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h2;
					end
				state9:
					begin
						num_count <= 20'd50;//230ns lcd_e enable//50
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b1;
						lcd_d  <= 4'h2;
					end
				state10:
					begin
						num_count <= 20'd3000;//3000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h2;
					end
				state11://function set,Entry Mode,Display Control,Display Clear or Data
					begin
						num_count <= 20'd10;//wait>40ns for setup time//10
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b0;
						lcd_d  <= wr_data[7:4];
					end
				state12:
					begin
						num_count <= 20'd50;//50
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b1;
						lcd_d  <= wr_data[7:4];
					end
				state13:
					begin
						num_count <= 20'd10;//wait>10ns for neg edge
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b0;
						lcd_d  <= wr_data[7:4];
					end
				state14:
					begin
						num_count <= 20'd100;//wait>1us between two 4-bits transfers//100
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b0;
						lcd_d  <= wr_data[3:0];
					end
				state15:
					begin
						num_count <= 20'd50;//50
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b1;
						lcd_d  <= wr_data[3:0];
					end
				state16:
					begin
						num_count <= 20'd3000;//10ns for neg edge and 40us for space between two communications//3000
						lcd_rs <= lcd_rs_define;
						lcd_e  <= 1'b0;
						lcd_d  <= wr_data[3:0];
					end
				state17:
					begin
						num_count <= 20'd90000;//1.64ms for display clear//82000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h0;
					end
				default
					begin
						num_count <= 20'd90000;//82000
						lcd_rs <= 1'b0;
						lcd_e  <= 1'b0;
						lcd_d  <= 4'h3;
					end
			endcase
			
//Revise delay count
	always @ (posedge clk or posedge reset)
		if (reset)
			delay_count <= 1'b1;
		else
			if (state_change)
				delay_count <= 1'b1;
		else
			if (delay_count <= 20'd1000000)
				delay_count <= delay_count + 1'b1;

//Command and Data define (bug in two susceptivity signals)
	always @ (posedge clk or posedge reset)
		if (reset)
			begin
				lcd_rs_define <= 1'b0;//command
				wr_data <= 8'h28;
			end
		else
			case (num_cm_da)
				4'd0 : begin wr_data <= 8'h28; lcd_rs_define <= 1'b0; end
				4'd1 : wr_data <= 8'h06;
				4'd2 : wr_data <= 8'h0C;
				4'd3 : wr_data <= 8'h01;
				4'd4 : begin wr_data <= 8'h87; lcd_rs_define <= 1'b0; end
				4'd5 : begin wr_data <= 8'h43; lcd_rs_define <= 1'b1; end
				default : begin wr_data <= 8'h0; lcd_rs_define <= 1'b0; end				
			endcase
									
endmodule