frequency_counter.vhd

晶振频率实时显示在LCD上,包含LCD驱动等程序.

-- Reference design - Frequency counter for Spartan-3E Starter Kit (Rev.C).
--
-- Ken Chapman - Xilinx Ltd - 7th March 2006
--
--  *** This design contains an evaluation test feature of the DCM. ****
--  *** Before this design can be processed a special environment   ****
--  *** needs to be set or the 'dcm_fixed_osc' module removed.      ****
--  *** Please read the notes provided in 'dcm_fixed_osc.vhd' for   ****
--  *** details of this special requirement.                        ****
--
--
-- Provides a frequency counter with resolution of 1Hz up to a maximum frequency of 
-- approximately 200MHz (limited by maximum clock rate of design).
--
-- The 50MHz on board oscillator is used to provide a 1 second time base and therefore 
-- defines the accuracy of the measurement. If the frequency of the 50MHz oscillator can 
-- be determined using a calibrated frequency counter or frequency generator then this design 
-- could be tuned to match the particular board. 
--
-- Slide switches SW0, SW1, SW2 and SW3 allow selection of the input signal or one of three test 
-- signals. Only one switch should be selected and the LCD display will guide and confirm the 
-- selection process.
--
-- SW0 selects SMA connector (J17) as the input signal to be analysed. 
-- SW1 selects the 50MHz oscillator as a test signal and must yield a perfect result since it is 
--     also the definition of the measurement time base..
-- SW2 selects a signal of approximately 145MHz which is generated by one of the DCMs operating 
--     in a special test oscillator mode.
-- SW3 selects a ring oscillator implement using a combinatorial loop in the CLB fabric. 
--
-- LED indicate measurements in progress (1 second alternate flashing of 4 LEDs).
--
-- PicoBlaze performs calculations and conversions as well as driving the LCD display.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2006.   This code may be contain portions patented by other 
-- third parties.  By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard 
-- is free from any claims of infringement by any third party.  Xilinx expressly 
-- disclaims any warranty with respect to the adequacy of the implementation, including 
-- but not limited to any warranty or representation that the implementation is free 
-- from claims of any third party.  Furthermore, Xilinx is providing this core as a 
-- courtesy to you and suggests that you contact all third parties to obtain the 
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
--
entity frequency_counter is
    Port (             led : out std_logic_vector(7 downto 0);
                        sw : in std_logic_vector(3 downto 0);
            strataflash_oe : out std_logic;
            strataflash_ce : out std_logic;
            strataflash_we : out std_logic;
                     lcd_d : inout std_logic_vector(7 downto 4);
                    lcd_rs : out std_logic;
                    lcd_rw : out std_logic;
                     lcd_e : out std_logic;
                   sma_clk : in std_logic;
                 clk_50mhz : in std_logic);
    end frequency_counter;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of frequency_counter is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
  component kcpsm3 
    Port (      address : out std_logic_vector(9 downto 0);
            instruction : in std_logic_vector(17 downto 0);
                port_id : out std_logic_vector(7 downto 0);
           write_strobe : out std_logic;
               out_port : out std_logic_vector(7 downto 0);
            read_strobe : out std_logic;
                in_port : in std_logic_vector(7 downto 0);
              interrupt : in std_logic;
          interrupt_ack : out std_logic;
                  reset : in std_logic;
                    clk : in std_logic);
    end component;
--
-- declaration of program ROM used by data capture processor
--
  component fc_ctrl
    Port (      address : in std_logic_vector(9 downto 0);
            instruction : out std_logic_vector(17 downto 0);
             proc_reset : out std_logic;                       --JTAG Loader version
                    clk : in std_logic);
    end component;

--
-- Fixed frequency oscillator using a DCM
--
component dcm_fixed_osc 
  port(    clk_out : out std_logic;
        kick_start : in std_logic   );
  end component;  

--
-- Ring oscillator
--
component ring_osc
  port(   osc_out : out std_logic;
            reset : in std_logic   );
   end component;  

--
------------------------------------------------------------------------------------
--
-- Signals used to select and provide sources to be analysed
--
signal source_control          : std_logic_vector(7 downto 0);
signal dcm_oscillator          : std_logic;
signal ring_oscillator         : std_logic;
signal freq_for_measurement    : std_logic;
signal test_clk                : std_logic;
--
--
--
--
-- Signals used by clock cycle counters and controls
--
signal ab_switch_delay         : std_logic_vector (3 downto 0);
signal a_count_ce              : std_logic;
signal a_count_rst             : std_logic;
signal a_count                 : std_logic_vector (31 downto 0);
signal b_count_ce              : std_logic;
signal b_count_rst             : std_logic;
signal b_count                 : std_logic_vector (31 downto 0);
--
--
--
-- Signals for 1 second interrupt generation and counter switching
--
signal one_second_count       : integer range 0 to 49999999 :=0;
signal one_second_pulse       : std_logic;
signal ab_switch              : std_logic;
signal interrupt_delay        : std_logic_vector (99 downto 0);
--
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address        : std_logic_vector(9 downto 0);
signal instruction    : std_logic_vector(17 downto 0);
signal port_id        : std_logic_vector(7 downto 0);
signal out_port       : std_logic_vector(7 downto 0);
signal in_port        : std_logic_vector(7 downto 0);
signal write_strobe   : std_logic;
signal read_strobe    : std_logic;
signal interrupt      : std_logic;
signal interrupt_ack  : std_logic;
signal reset          : std_logic;
--
--
-- Signals for LCD operation
--
-- Tri-state output requires internal signals
-- 'lcd_drive' is used to differentiate between LCD and StrataFLASH communications 
-- which share the same data bits.
--
signal   lcd_rw_control : std_logic;
signal  lcd_output_data : std_logic_vector(7 downto 4);
signal        lcd_drive : std_logic;
--
--
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
  --
  --
  ----------------------------------------------------------------------------------------------------------------------------------
  -- Disable unused components  
  ----------------------------------------------------------------------------------------------------------------------------------
  --
  --StrataFLASH must be disabled to prevent it conflicting with the LCD display 
  --
  strataflash_oe <= '1';
  strataflash_ce <= '1';
  strataflash_we <= '1';
  --
  --
  ----------------------------------------------------------------------------------------------------------------------------------
  -- Select and Buffer signal to be analysed
  ----------------------------------------------------------------------------------------------------------------------------------
  --
  -- 
  -- The fixed frequency dcm oscillator using test mode of the DCM
  --
  dcm_fixed_oscillator: dcm_fixed_osc
  port map (    clk_out => dcm_oscillator,
             kick_start => source_control(7) );

  -- 
  -- ring Oscillator using logic fabric 
  --

  logic_oscillator: ring_osc
  port map (   osc_out => ring_oscillator,
                 reset => source_control(6) );

  -- 
  -- Source selection multiplexer (must be combinatorial) 
  --

  freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00") 
                     else clk_50mhz when (source_control(1 downto 0)="01") 
                     else dcm_oscillator when (source_control(1 downto 0)="10") 
                     else ring_oscillator;


  -- 
  -- Global buffer on selected source 
  --

  buffer_clkin: BUFG
  port map( O => test_clk,
            I => freq_for_measurement);

  --
  ----------------------------------------------------------------------------------------------------------------------------------
  -- Frequency Counters
  --
  -- This is formed of two simple 32-bit binary counters such that one can be counting whilst the 
  -- other is being read and reset. Great care is taken to ensure the switch over between the two