📄 ccxx.c
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#include "hal.h"
BYTE rfSettings[]= {
0x06, // IOCFG2 Y
0x2E, // IOCFG1 Y
0x06, // IOCFG0D Y
0x07, // FIFOTHR Y
0xD3, // SYNC1 Y
0x91, // SYNC0 Y
0x02, // PKTLEN Y 0xFF
0x04, // pktctrl1
0x04, // pktctrl0 0x05 fixed length
0x00, // addr Y
0x00, // CHANNR Y
0x0A, // FSCTRL1 Frequency synthesizer control.0X17 0x0c
0x00, // FSCTRL0 Frequency synthesizer control.
0x5D, // FREQ2 Frequency control word, high byte.
0x93, // FREQ1 Frequency control word, middle byte.
0xB1, // FREQ0 Frequency control word, low byte.
0x78, // MDMCFG4 Modem configuration. x2D 0x0e
0x93, // MDMCFG3 Modem configuration.
0x03, // MDMCFG2 Modem configuration.
0x02, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x44, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0x07, // MCSM2
0x00, // MCSM1
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x16, // FOCCFG Frequency Offset Compensation Configuration.
0x6C, // BSCFG Bit synchronization Configuration.
0x43, // AGCCTRL2 AGC control.
0x40, // AGCCTRL1 AGC control.
0x91, // AGCCTRL0 AGC control.
0x87, // WOREVT1
0x6b, // WOREVT0
0xf8, // WORCTRL
0x56, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0xA9, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.(38)
0x41, // RCCTRL1 Y
0x00, // RCCTRL0 Y
0x59, // FSTEST Y
0x7F, // PTEST Y
0x3F, // AGCTEST Y
0x88, // TEST2 Y
0x31, // TEST1 Y
0x0B // TEST0 Y
};
/*
*********************************************************************************************************
* CCxx_init
*
* Description :
* Arguments :
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
void CCxx_init(void)
{
BYTE RfPa[8] = {0xFF ,0xFF ,0xFF ,0xFF ,0xFF ,0xFF ,0xFF ,0xFF};
SET_CSN;
Pause_10uS(4);
CLR_CSN;
Pause_10uS(4);
SET_CSN;
Pause_10uS(6);
CLR_CSN;
while (SOREAD);
SpiStrobe(CCxxx0_SRES);
SET_CSN;
SpiWriteBurstReg(0x00,rfSettings,0x2F);
SpiWriteBurstReg(CCxxx0_PATABLE, RfPa, 1);
}
/*
*********************************************************************************************************
* CCxx_send
*
* Description :
* Arguments :
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
void CCxx_send(BYTE *buf, BYTE n)
{
SpiWriteBurstReg(CCxxx0_TXFIFO, buf, n);
SpiStrobe(CCxxx0_STX);
while (!GDO2READ);
while (GDO2READ);
}
/*
*********************************************************************************************************
* CCxx_receive
*
* Description :
* Arguments :
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
BOOL CCxx_receive(BYTE *buf, BYTE *n)
{
BYTE status[2];
SpiStrobe(CCxxx0_SRX);
while (!GDO2READ);
while (GDO2READ);
if ((SpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) {
SpiReadBurstReg(CCxxx0_RXFIFO, buf, 2);
SpiReadBurstReg(CCxxx0_RXFIFO, status, 2);
return (status[LQI] & CRC_OK);
}else{
return 0;
}
}
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