st16954sio.h

vxworks下串口驱动如何开发 主要针对16c954的非智能串口的初始化和 收发数据

/* st16954Sio.h - Startech (Exar) 16954 DUART header file */
/* weiheying 2004,06,10 */

#ifndef __INCst16954Sioh
#define __INCst16954Sioh

#ifdef __cplusplus
extern "C" {
#endif

/* REGISTER DESCRIPTION OF STARTECH 16954 DUART */

#ifndef _ASMLANGUAGE


/* Register offsets from base address */

#define RHR	0x00	/* Receive Holding Register (R/O) */
#define THR	0x00	/* Transmit Holding Register (W/O)*/
#define IER	0x01	/* Interrupt Enable Register */
#define ISR	0x02	/* Interupt Status Register (R/O) */
#define FCR	0x02	/* FIFO Control register (W/O) */
#define LCR	0x03	/* Line Control Register */
#define MCR	0x04	/* Modem Control Register */
#define LSR	0x05	/* Line Status register */
#define MSR	0x06	/* Modem Status Register */
#define SPR	0x07	/* Scratchpad Register */

/* Additional Standard Registers
 * These registers require divisor latch access bit (LCR[7]) to be set to 1.
*/
#define DLL	0x00	/* Divisor Latch Low */
#define DLM	0x01	/* Divisor Latch Middle */

/* To access these registers LCR must be set to 0xBF */

#define EFR	0x02	/* Enhanced Features Register */
#define XON1	0x04	
#define XON2	0x05	
#define XOFF1	0x06	
#define XOFF2	0x07	

/* Specific Registers */

#define ASR	0x01	/* Additional Status Register */
#define RFL	0x03	/* Number of characters in the receiver FIFO */
#define TFL	0x04	/* Number of characters in the transmitter FIFO */
#define ACR	0x05	/* Indexed Control Register */
#define TTL	0x05        /* Transmitter Trigger Level Register */
#define RTL	0x05        /* Receiver Trigger Level Register */
#define FCL	0x05        /* Flow Control Levels Register */
#define FCH	0x05        /* Flow Control Levels Register */
#define CSR   0x05         /* Channel Software Reset Register */
#define REV   0x05         /* Reversion Register */

/* SPR Offset of Indexed Control Register Set */

#define SPR_ACR   0x00         /* Additional Control Register Offset */
#define SPR_CPR   0x01         /* Clock Prescaler Register Offset */
#define SPR_TCR   0x02         /* Times Clock Register Offset */
#define SPR_CKS   0x03         /* Clock Select Register Offset */
#define SPR_TTL   0x04         /* Transmitter Trigger Level Register Offset */
#define SPR_RTL   0x05         /* Receiver Trigger Level Register Offset */
#define SPR_FCL   0x06         /* Flow Control Levels Register Offset */
#define SPR_FCH   0x07         /* Flow Control Levesl Register Offset */
#define SPR_ID1   0x08         /* Device Identification 1 Register Offset */
#define SPR_ID2   0x09         /* Device Identification 2 Register Offset */
#define SPR_ID3   0x0A         /* Device Identification 3 Register Offset */
#define SPR_REV   0x0B         /* Reversion Register Offset */
#define SPR_CSR   0x0C         /* Channel Software Reset Register Offset */
#define SPR_NMR   0x0D         /* Nine-bit Mode Register Offset */
#define SPR_MDM   0x0E         /* Modem Disable Mask Register Offset */
#define SPR_RFC   0x0F         /* Readable FCR Register Offset */
#define SPR_GDS   0x10         /* Good-data status Register Offset */
#define SPR_DMS   0x11         /* DMA Status Register Offset */
#define SPR_PIDX   0x12         /* Port Index Register Offset */
#define SPR_CKA   0x13         /* Clock Alteration Register Offset */

#define BAUD_LO(baud)  ((XTAL/(16*baud)) & 0xFF)
#define BAUD_HI(baud)  (((XTAL/(16*baud)) & 0xFF00) >> 8)

/* Line Control Register values */

#define LCR_EFREN      0xBF      /* enable EFR */
#define CHAR_LEN_5	0x00
#define CHAR_LEN_6	0x01
#define CHAR_LEN_7	0x02
#define CHAR_LEN_8	0x03
#define LCR_STB		0x04	/* Stop bit control (1.5/2) */
#define ONE_STOP	0x00	/* One stop bit! */
#define LCR_PEN		0x08	/* Parity Enable */
#define PARITY_NONE	0x00
#define LCR_OPS		0x10	/* Odd Parity Select */
#define LCR_EPS		0x10	/* Even Parity Select */
#define LCR_SP_1		0x20	/* Force Parity to 1 */
#define LCR_SP_0		0x30	/* Force Parity to 0 */
#define LCR_SBRK	        0x40	/* Start Break */
#define LCR_DLAB	        0x80	/* Divisor Latch Access Bit */
#define DLAB		LCR_DLAB

/* Line Status Register */

#define LSR_DR		0x01	/* Data Ready */
#define RxCHAR_AVAIL	LSR_DR
#define LSR_OE		0x02	/* Overrun Error */
#define LSR_PE		0x04	/* Parity Error */
#define LSR_FE		0x08	/* Framing Error */
#define LSR_BI		0x10	/* Received Break Signal */
#define LSR_THRE	        0x20	/* Transmit Holding Register Empty */
#define LSR_TEMT  	0x40	/* THR and FIFO empty */
#define LSR_FERR	        0x80	/* Parity, Framing error or break in FIFO */

/* Interrupt Status Register */

#define ISR_IP		0x01		/* Interrupt Pending */
#define ISR_ID		0x0E		/* Interrupt source mask */
#define ISR_RLS		0x06		/* Rx Line Status Int */
#define Rx_INT		ISR_RLS
#define ISR_RDA		0x04		/* Rx Data Available */
#define RxFIFO_INT	ISR_RDA
#define ISR_THRE	0x02		/* THR Empty */
#define TxFIFO_INT	ISR_THRE
#define ISR_MSTAT	0x00		/* Modem Status Register Int */
#define ISR_TIMEOUT	0x0C		/* Rx Data Timeout */

/* Interrupt Enable Register */

#define IER_ERDAI	        0x01		/* Enable Rx Data Available Int */
#define RxFIFO_BIT	IER_ERDAI
#define IER_ETHREI	0x02		/* Enable THR Empty Int */
#define TxFIFO_BIT	IER_ETHREI
#define IER_ELSI	0x04		/* Enable Line Status Int */
#define Rx_BIT		IER_ELSI
#define IER_EMSI	0x08		/* Enable Modem Status Int */

/* Modem Control Register */

#define MCR_DTR		0x01		/* state of DTR output */
#define DTR		MCR_DTR
#define MCR_RTS		0x02		/* state of RTS output */
#define MCR_OUT1	0x04		/* UNUSED in ST16954 */
#define MCR_INT		0x08		/* Int Mode */
#define MCR_LOOP	0x10		/* Enable Loopback mode */

/* Modem Status Register */

#define MSR_DCTS	0x01		/* change in CTS */
#define MSR_DDSR	0x02		/* change in DSR */
#define MSR_TERI 	0x04		/* change in RI */
#define MSR_DDCD	0x08		/* change in DCD */
#define MSR_CTS		0x10		/* state of CTS input */
#define MSR_DSR		0x20		/* state of DSR input */
#define MSR_RI		0x40		/* state of RI input */
#define MSR_DCD		0x80		/* state of DCD input */

/* FIFO Control Register */

#define FCR_EN		0x01		/* FIFO Enable */
#define FIFO_ENABLE	FCR_EN
#define FCR_RXCLR	0x02		/* Rx FIFO Clear */
#define RxCLEAR		FCR_RXCLR
#define FCR_TXCLR	0x04		/* Tx FIFO Clear */
#define TxCLEAR		FCR_TXCLR
#define FCR_DMA		0x08		/* FIFO Mode Control */
#define FCR_RXTRIG_L	0x40		/* FIFO Trigger level Low */
#define FCR_RXTRIG_H	0x80		/* FIFO Trigger level High */

/* Enhanced Features Register */

#define EFR_ENM          0x10                /* Enhanced mode */
#define EFR_ESCD        0x20                /* Enable special character detection */
#define EFR_RTSEN      0x40                /* Enable automatic RTS flow control */
#define EFR_CTSEN      0x80                /* Enable automatic CTS flow control */

/* Indexed Control Register */

#define ACR_RXDIS	0x01                 /* Receiver diable */
#define ACR_TXDIS	0x02                 /* Transmitter diable */
#define ACR_DSR	        0x04                 /* Enable automatic DSR flow control */
#define ACR_950     	0x20                 /* 950 mode trigger levels enable */
#define ACR_ICREN	0x40                 /* ICR read enable */
#define ACR_ADDEN	0x80                 /* Additional status enable */

typedef struct st16954_chan		/* ST16954_CHAN */
    {
    /* must be first */

    SIO_CHAN	sio;			/* standard SIO_CHAN element */

    /* callbacks */

    STATUS	(*getTxChar) ();	/* installed Tx callback routine */
    STATUS	(*putRcvChar) ();	/* installed Rx callback routine */
    void *	getTxArg;		/* argument to Tx callback routine */
    void *	putRcvArg;		/* argument to Rx callback routine */

    UINT8 *	regs;			/* ST16954 registers */
    UINT8	level;			/* Interrupt level for this device */
    UINT8	ier;			/* copy of IER */
    UINT8	lcr;			/* copy of LCR */
    UINT16 fifosize;            /* fifo size 0-127*/
    UINT8 mode;               /* 0-normal mode; 1-loop mode */

    UINT32	channelMode;		/* such as INT, POLL modes */
    UINT32	regDelta;		/* register address spacing */
    int		baudRate;		/* the current baud rate */
    UINT32	xtal;			/* UART clock frequency */

    } ST16954_CHAN;


/* structure used as parameter to multiplexed interrupt handler */

typedef struct st16954_mux		/* ST16954_MUX */
    {
    int			nextChan;	/* next channel to examine on int */
    ST16954_CHAN *	pChan;		/* array of ST16954_CHAN structs */
    } ST16954_MUX;



/* local defines  */

#ifndef ST16954_REG_READ
#define ST16954_REG_READ(pChan, reg, result) \
	result = \
	    (*(volatile UINT8 *)((UINT32)pChan->regs + (reg*pChan->regDelta)))
#endif

#ifndef ST16954_REG_WRITE
#define ST16954_REG_WRITE(pChan, reg, data) \
	(*(volatile UINT8 *)((UINT32)pChan->regs + (reg*pChan->regDelta))) = \
		(data)
#endif

/* function declarations */
extern void st16954Int (ST16954_CHAN *);
extern void st16954MuxInt(ST16954_MUX *);
extern void st16954DevInit (ST16954_CHAN *);

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCst16954Sioh */