📄 mx21_pagetable.c
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/**********************************************************************
*
* (C) COPYRIGHT 2004 FREESCALE, INC.
* ALL RIGHTS RESERVED
*
*
* Group/Division: WMSG/MMDO
*
* Description:
*
* Related Specifications:
*
* Errata:
*
* File Name: MX21_PageTable.c
* Revision Number: 0.1
* Author(s): Sharad Kumar
* Date created:
* Revision History:
* Date Rev Description
* ---- --- -----------
* 30Apr2004 0.1 First Draft
*
**********************************************************************/
#include <stdio.h>
#include "MX21_DataTypes.h"
#include "MX21_PageTable.h"
//---------------------------------------------------
// setup the pagetable. All first level descriptors are sections.
// The default vector table address is remapped to an SDRAM
// location, as there is ROM at 0x0.
//---------------------------------------------------
unsigned long const*
ARM_MMUTableSetUp(void)
{
// local variables
uint32_t i;
unsigned long *p = &pagetable[0];
// remap default vector table jump address
// to an SDRAM location (0xC0000000)
// with attributes of non cacheable and non bufferable
*(p++) = (MMU_SDRAM_BASE_ADDR | MMU_TYPE_SECTION | MMU_PERMISSIONS | MMU_SET_BIT4 |
MMU_CACHEABLE | MMU_BUFFERABLE);
// set up contiguous sections in the
// page tables.
for(i=1; i < MMU_PAGE_ENTRIES; i++)
{
// Registers, EIM, PCMCIA, NAND Flash are
// non cacheable, non bufferable
if((MMU_REG_OFFST == i) || (MMU_EIM_OFFST == i)) {
// left shift by 20 provides a
// 1 MB offset.
*(p++) = ((i << 20) | MMU_TYPE_SECTION | MMU_PERMISSIONS | MMU_SET_BIT4);
}
else {
*(p++) = ((i << 20) | MMU_TYPE_SECTION | MMU_PERMISSIONS |
MMU_SET_BIT4 | MMU_CACHEABLE | MMU_BUFFERABLE) | MMU_SET_BIT4;
}
}
// return the base address
// of the pagetables
return pagetable;
}
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