mx21_crm.c

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

//SPLL_Lock
 void
pllclk_SPLL_Lock(void)
{
 PLLCLK_SPCTL1.bits.LF=1;
 return;
}


//SPLL_Unlock
 void
pllclk_SPLL_Unlock(void)
{
 PLLCLK_SPCTL1.bits.LF=0;
 return;
}


//SPLL_BRM_FirstOrder
 void
pllclk_SPLL_BRM_FirstOrder(void)
{
 PLLCLK_SPCTL1.bits.BRMO=0;
 return;
}


//SPLL_BRM_SecondOrder
 void
pllclk_SPLL_BRM_SecondOrder(void)
{
 PLLCLK_SPCTL1.bits.BRMO=1;
 return;
}


//OSC26M_AutomaticGainControl
 void
pllclk_OSC26M_AutomaticGainControl(uint32_t AGC)
{
 PLLCLK_OSC26MCTL.bits.AGC=AGC;
 return;
}


//OSC26M_AmplitudeCheck
 uint32_t
pllclk_OSC26M_AmplitudeCheck(void)
{
 return PLLCLK_OSC26MCTL.bits.OSC26M_PEAK;
}


//OSC26M_AutoTrim
uint32_t
pllclk_OSC26M_AutoTrim(void)
{
 uint32_t _trim=0x3F;
 pllclk_OSC26M_AutomaticGainControl(_trim);
 while(_trim>3){
  gpt3_WaitTime(31);
  if(pllclk_OSC26M_AmplitudeCheck()==3){
   pllclk_OSC26M_AutomaticGainControl(0x3F);
   return 0xFFFFFFFF;
  } else if (pllclk_OSC26M_AmplitudeCheck()==0){
   _trim-=4;
   pllclk_OSC26M_AutomaticGainControl(_trim);
   return _trim;
  } else {
   pllclk_OSC26M_AutomaticGainControl(--_trim);
  }
 }
 gpt3_WaitTime(31);
 pllclk_OSC26M_AutomaticGainControl(0);
 gpt3_WaitTime(31);
 if(pllclk_OSC26M_AmplitudeCheck()==0){
  return 0;
 } else {
  pllclk_OSC26M_AutomaticGainControl(0x3F);
  return 0xFFFFFFFF;
 }
}


//SSI2_Divider
 void
pllclk_SSI2_Divider(uint32_t SSI2DIV)
{
 PLLCLK_PCDR0.bits.SSI2DIV=SSI2DIV;
 return;
}


//SSI1_Divider
 void
pllclk_SSI1_Divider(uint32_t SSI1DIV)
{
 PLLCLK_PCDR0.bits.SSI1DIV=SSI1DIV;
 return;
}


//SSI2_AutoDivider
uint32_t
pllclk_SSI2_AutoDivider(uint32_t divider)
{

// FIX ME 
 return 0;
}

//SSI1_AutoDivider
uint32_t
pllclk_SSI1_AutoDivider(uint32_t divider)
{

// FIX ME 
 return 0;
}


//NFC_Divider
 void
pllclk_NFC_Divider(uint32_t NFCDIV)
{
 PLLCLK_PCDR0.bits.NFCDIV=NFCDIV;
 return;
}


//CLKO48M_Divider
 void
pllclk_CLKO48M_Divider(uint32_t CLKO_48MDIV)
{
 PLLCLK_PCDR0.bits.CLKO_48MDIV=CLKO_48MDIV;
 return;
}


//FIRI_Divider
 void
pllclk_FIRI_Divider(uint32_t FIRI_DIV)
{
 PLLCLK_PCDR0.bits.FIRI_DIV=FIRI_DIV;
 return;
}


//PERCLK4_Divider
 void
pllclk_PERCLK4_Divider(uint32_t PERDIV4)
{
 PLLCLK_PCDR1.bits.PERDIV4=PERDIV4;
 return;
}


//PERCLK3_Divider
 void
pllclk_PERCLK3_Divider(uint32_t PERDIV3)
{
 PLLCLK_PCDR1.bits.PERDIV3=PERDIV3;
 return;
}


//PERCLK2_Divider
 void
pllclk_PERCLK2_Divider(uint32_t PERDIV2)
{
 PLLCLK_PCDR1.bits.PERDIV2=PERDIV2;
 return;
}


//PERCLK1_Divider
 void
pllclk_PERCLK1_Divider(uint32_t PERDIV1)
{
 PLLCLK_PCDR1.bits.PERDIV1=PERDIV1;
 return;
}


//CSI_HCLK
 void
pllclk_CSI_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_CSI_EN=EN;
 return;
}

//DMA_HCLK
 void
pllclk_DMA_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_DMA_EN=EN;
 return;
}

//BROM_HCLK
 void
pllclk_BROM_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_BROM_EN=EN;
 return;
}

//EMMA_HCLK
 void
pllclk_EMMA_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_EMMA_EN=EN;
 return;
}

//LCDC_HCLK
 void
pllclk_LCDC_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_LCDC_EN=EN;
 return;
}

//SLCDC_HCLK
 void
pllclk_SLCDC_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_SLCDC_EN=EN;
 return;
}


//USB_HCLK
 void
pllclk_USB_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_USBOTG_EN=EN;
 return;
}


//BMI_HCLK
 void
pllclk_BMI_HCLK(uint32_t EN)
{
 PLLCLK_PCCR0.bits.HCLK_BMI_EN=EN;
 return;
}


//CSI_Clk
 void
pllclk_CSI_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.PERCLK4_EN=EN;
 return;
}


//SLCDC_Clk
 void
pllclk_SLCDC_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SLCDC_EN=EN;
 return;
}


//FIRI_BAUD_Clk
 void
pllclk_FIRI_BAUD_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.FIRI_BAUD_EN=EN;
 return;
}


//NFC_Clk
 void
pllclk_NFC_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.NFC_EN=EN;
 return;
}


//LCDC_Clk
 void
pllclk_LCDC_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.PERCLK3_EN=EN;
 return;
}


//SSI1_BAUD_Clk
 void
pllclk_SSI1_BAUD_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SSI1_BAUD_EN=EN;
 return;
}


//SSI2_BAUD_Clk
 void
pllclk_SSI2_BAUD_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SSI2_BAUD_EN=EN;
 return;
}


//EMMA_Clk
 void
pllclk_EMMA_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.EMMA_EN=EN;
 return;
}


//USB_Clk
 void
pllclk_USB_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.USBOTG_EN=EN;
 return;
}


//DMA_Clk
 void
pllclk_DMA_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.DMA_EN=EN;
 return;
}


//I2C_Clk
 void
pllclk_I2C_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.I2C_EN=EN;
 return;
}


//GPIO_Clk
 void
pllclk_GPIO_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.GPIO_EN=EN;
 return;
}


//SDHC2_Clk
 void
pllclk_SDHC2_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SDHC2_EN=EN;
 return;
}


//SDHC1_Clk
 void
pllclk_SDHC1_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SDHC1_EN=EN;
 return;
}


//FIRI_Clk
 void
pllclk_FIRI_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.FIRI_EN=EN;
 return;
}


//SSI2_Clk
 void
pllclk_SSI2_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SSI2_EN=EN;
 return;
}


//SSI1_Clk
 void
pllclk_SSI1_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.SSI1_EN=EN;
 return;
}


//CSPI2_Clk
 void
pllclk_CSPI2_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.CSPI2_EN=EN;
 return;
}


//CSPI1_Clk
 void
pllclk_CSPI1_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.CSPI1_EN=EN;
 return;
}


//UART4_Clk
 void
pllclk_UART4_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.UART4_EN=EN;
 return;
}


//UART3_Clk
 void
pllclk_UART3_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.UART3_EN=EN;
 return;
}


//UART2_Clk
 void
pllclk_UART2_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.UART2_EN=EN;
 return;
}


//UART1_Clk
 void
pllclk_UART1_Clk(uint32_t EN)
{
 PLLCLK_PCCR0.bits.UART1_EN=EN;
 return;
}


//OWIRE_Clk
 void
pllclk_OWIRE_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.OWIRE_EN=EN;
 return;
}


//KPP_Clk
 void
pllclk_KPP_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.KPP_EN=EN;
 return;
}


//RTC_Clk
 void
pllclk_RTC_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.RTC_EN=EN;
 return;
}


//PWM_Clk
 void
pllclk_PWM_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.PWM_EN=EN;
 return;
}


//GPT3_Clk
 void
pllclk_GPT3_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.GPT3_EN=EN;
 return;
}


//GPT2_Clk
 void
pllclk_GPT2_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.GPT2_EN=EN;
 return;
}


//GPT1_Clk
 void
pllclk_GPT1_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.GPT1_EN=EN;
 return;
}


//WDT_Clk
 void
pllclk_WDT_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.WDT_EN=EN;
 return;
}


//CSPI3_Clk
 void
pllclk_CSPI3_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.CSPI3_EN=EN;
 return;
}


//RTIC_Clk
 void
pllclk_RTIC_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.RTIC_EN=EN;
 return;
}


//RNGA_Clk
 void
pllclk_RNGA_Clk(uint32_t EN)
{
 PLLCLK_PCCR1.bits.RNGA_EN=EN;
 return;
}


//32K_ClkStatus
 uint32_t
pllclk_32K_ClkStatus(void)
{
 return PLLCLK_CCSR.bits.SR_32K;
}

//CLKO_Select
 void
pllclk_CLKO_Select(uint32_t CLKO_SEL)
{
 PLLCLK_CCSR.bits.CLKO_SEL=CLKO_SEL;
 return;
}

//WakeupGuardModeEnable
 void
pllclk_WakeupGuardModeEnable(void)
{
 PLLCLK_WKGDCTL.bits.WKDG_EN=1;
 return;
}