mx21_crm.c

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division:  WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name:        MX21_CRM.c
*     Revision Number:  0.1
*     Author(s):        Ryan Johnson
*     Date created:     23 June 2004
*     Revision History:
*        Date      Rev     Description
*        ----      ---     -----------
*        23June04  0.1     First draft
*        12July04  0.2     Clk Freq functions & tweaking
*
**********************************************************************/

#include "MX21_CRM.h"


extern void gpt3_WaitTime(uint32_t microseconds);

//MPLL_SetFrequency
uint32_t
pllclk_MPLL_SetFrequency(uint32_t frequency)
{
 //'thorough', non-fp
 uint32_t _refclock, _PD, _MF, _MFI, _MFN, _MFD=1023, _CLOCK, _MFNTEMP, _MFDTEMP, _MFTEMP;

 if(!PLLCLK_CSCR.bits.MCU_SEL){
  _refclock=_32K;
 } else {
  if(PLLCLK_CSCR.bits.OSC26M_DIV1P5){
   _refclock=_26M*2/3;
  } else {
   _refclock=_26M;
  }
 }

 _PD = 2*_refclock*16/frequency;

 if(2*_refclock*16%frequency==0){
  _PD-=1;
 }
 _CLOCK = 2*_refclock;
 _refclock/=_PD;
 _MFI=frequency/(2*_refclock);
 _MF = (frequency/2) % _refclock;
 _MFN = _MF*256/_refclock;
 _MFN*=4;
 _MFN+=3;
 if(_MFN==1023){
  _MFN-=1;
 } 
 _refclock/=4;
 _MF/=4;
 _MFDTEMP=_MFD; 
 for(_MFNTEMP=_MFN;_MFNTEMP>0;){
  _MFTEMP=_refclock*_MFNTEMP/_MFDTEMP;
  if(abs(_MFTEMP - _MF) < abs(_refclock*_MFN/_MFD - _MF)){
   _MFN=_MFNTEMP;
   _MFD=_MFDTEMP;
  }
  if(_MFTEMP > _MF){
   _MFNTEMP-=1;
  } else if (_refclock*_MFNTEMP/_MFDTEMP < _MF){
   _MFDTEMP-=1;
  } else {
   break;
  } 
 } 
 pllclk_MPLL_Predivider(_PD - 1);
 pllclk_MPLL_Multiplier_Integer(_MFI);
 pllclk_MPLL_Multiplier_Denominator(_MFD-1);
 pllclk_MPLL_Multiplier_Numerator(_MFN); 
 _CLOCK= _CLOCK*(_MFI + 1.0*_MFN/_MFD)/_PD;
 return _CLOCK;
}

//SPLL_SetFrequency
uint32_t
pllclk_SPLL_SetFrequency(uint32_t frequency)
{
 //'thorough', non-fp
 uint32_t _refclock, _PD, _MF, _MFI, _MFN, _MFD=1023, _CLOCK, _MFNTEMP, _MFDTEMP, _MFTEMP;

 if(!PLLCLK_CSCR.bits.MCU_SEL){
  _refclock=_32K;
 } else {
  if(PLLCLK_CSCR.bits.OSC26M_DIV1P5){
   _refclock=_26M*2/3;
  } else {
   _refclock=_26M;
  }
 }
 _PD = 2*_refclock*16/frequency;
 if(2*_refclock*16%frequency==0){
  _PD-=1;
 }
 _CLOCK = 2*_refclock;
 _refclock/=_PD;
 _MFI=frequency/(2*_refclock);
 _MF = (frequency/2) % _refclock;
 _MFN = _MF*256/_refclock;
 _MFN*=4;
 _MFN+=3;
 if(_MFN==1023){
  _MFN-=1;
 }
 _refclock/=4;
 _MF/=4;
 _MFDTEMP=_MFD; 
 for(_MFNTEMP=_MFN;_MFNTEMP>0;){
  _MFTEMP=_refclock*_MFNTEMP/_MFDTEMP;
  if(abs(_MFTEMP - _MF) < abs(_refclock*_MFN/_MFD - _MF)){
   _MFN=_MFNTEMP;
   _MFD=_MFDTEMP;
  }
  if(_MFTEMP > _MF){
   _MFNTEMP-=1;
  } else if (_refclock*_MFNTEMP/_MFDTEMP < _MF){
   _MFDTEMP-=1;
  } else {
   break;
  } 
 } 
 pllclk_SPLL_PD(_PD - 1);
 pllclk_SPLL_Multiplier_Integer(_MFI);
 pllclk_SPLL_Multiplier_Denominator(_MFD - 1);
 pllclk_SPLL_Multiplier_Numerator(_MFN); 
 _CLOCK= _CLOCK*(_MFI + 1.0*_MFN/_MFD)/_PD;
 return _CLOCK;
}

//MPLL_Frequency
 uint32_t
pllclk_MPLL_Frequency(void){
 uint32_t _refclock;
 uint32_t _MFI=PLLCLK_MPCTL0.bits.MFI;
 uint32_t _MFN=PLLCLK_MPCTL0.bits.MFN;
 uint32_t _MFD=PLLCLK_MPCTL0.bits.MFD;
 uint32_t _PD=PLLCLK_MPCTL0.bits.PD;
 if(!PLLCLK_CSCR.bits.MCU_SEL){
  _refclock=_32K;
 } else {
  _refclock=_26M;
 }
 _refclock=2*_refclock*(_MFI + 1.0*_MFN/(_MFD + 1))/(_PD+1);
 return _refclock;
}
//SPLL_Frequency
 uint32_t
pllclk_SPLL_Frequency(void){
 uint32_t _refclock;
 uint32_t _MFI=PLLCLK_SPCTL0.bits.MFI;
 uint32_t _MFN=PLLCLK_SPCTL0.bits.MFN;
 uint32_t _MFD=PLLCLK_SPCTL0.bits.MFD;
 uint32_t _PD=PLLCLK_SPCTL0.bits.PD;
 if(!PLLCLK_CSCR.bits.SP_SEL){
  _refclock=_32K;
 } else {
  _refclock=_26M;
 }
 _refclock=2*_refclock*(_MFI + 1.0*_MFN/(_MFD + 1))/(_PD+1);
 return _refclock;
}
//FCLK_Frequency
 uint32_t
pllclk_FCLK_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_CSCR.bits.PRESC);
}
//HCLK_Frequency
 uint32_t
pllclk_HCLK_Frequency(void){
 return pllclk_FCLK_Frequency()/(PLLCLK_CSCR.bits.BCLKDIV);
}
//PERCLK_Frequency
 uint32_t
pllclk_PERCLK_Frequency(void){
 return pllclk_HCLK_Frequency()/(PLLCLK_CSCR.bits.IPDIV);
}
//PERCLK1_Frequency
 uint32_t
pllclk_PERCLK1_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_PCDR1.bits.PERDIV1);
}
//PERCLK2_Frequency
 uint32_t
pllclk_PERCLK2_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_PCDR1.bits.PERDIV2);
}
//PERCLK3_Frequency
 uint32_t
pllclk_PERCLK3_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_PCDR1.bits.PERDIV3);
}
//PERCLK4_Frequency
 uint32_t
pllclk_PERCLK4_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_PCDR1.bits.PERDIV4);
}
//FIRICLK_Frequency
uint32_t
pllclk_FIRICLK_Frequency(void){
 if(PLLCLK_CSCR.bits.FIR_SEL){
  return pllclk_SPLL_Frequency()/(PLLCLK_PCDR0.bits.FIRI_DIV);
 } else {
  return pllclk_MPLL_Frequency()/(PLLCLK_PCDR0.bits.FIRI_DIV);
 }
}
//CLK48M_Frequency
 uint32_t
pllclk_CLK48M_Frequency(void){
 return pllclk_MPLL_Frequency()/(PLLCLK_CSCR.bits.USB_DIV);
}
//SSI1CLK_Frequency
uint32_t
pllclk_SSI1CLK_Frequency(void){
 if(PLLCLK_CSCR.bits.SSI1_SEL){
  return pllclk_MPLL_Frequency()/(PLLCLK_PCDR0.bits.SSI1DIV);
 } else {
  return pllclk_SPLL_Frequency()/(PLLCLK_PCDR0.bits.SSI1DIV);
 }
}
//SSI2CLK_Frequency
uint32_t
pllclk_SSI2CLK_Frequency(void){
 if(PLLCLK_CSCR.bits.SSI2_SEL){
  return pllclk_MPLL_Frequency()/(PLLCLK_PCDR0.bits.SSI2DIV);
 } else {
  return pllclk_SPLL_Frequency()/(PLLCLK_PCDR0.bits.SSI2DIV);
 }
}

//SetPrescaler
 void 
pllclk_SetPrescaler(uint32_t PRESC)
{
 PLLCLK_CSCR.bits.PRESC=PRESC;
 return;
}


//USB_Divider
 void
pllclk_USB_Divider(uint32_t USB_DIV)
{
 PLLCLK_CSCR.bits.USB_DIV=USB_DIV;
 return;
}


//ShutdownControl
 void
pllclk_ShutdownControl(uint32_t SD_CNT)
{
 PLLCLK_CSCR.bits.SD_CNT=SD_CNT;
 return;
}


//SPLL_Restart
 void
pllclk_SPLL_Restart(void)
{
 PLLCLK_CSCR.bits.SPLL_RESTART=1;
 return;
}


//MPLL_Restart
 void
pllclk_MPLL_Restart(void)
{
 PLLCLK_CSCR.bits.MPLL_RESTART=1;
 return;
}


//SSI2_SPLL
 void
pllclk_SSI2_SPLL(void)
{
 PLLCLK_CSCR.bits.SSI2_SEL=0;
 return;
}


//SSI2_MPLL
 void
pllclk_SSI2_MPLL(void)
{
 PLLCLK_CSCR.bits.SSI2_SEL=1;
 return;
}


//SSI1_SPLL
 void
pllclk_SSI1_SPLL(void)
{
 PLLCLK_CSCR.bits.SSI1_SEL=0;
 return;
}


//SSI1_MPLL
 void
pllclk_SSI1_MPLL(void)
{
 PLLCLK_CSCR.bits.SSI1_SEL=1;
 return;
}


//FIRI_SPLL
 void
pllclk_FIRI_SPLL(void)
{
 PLLCLK_CSCR.bits.FIR_SEL=1;
 return;
}


//FIRI_MPLL
 void
pllclk_FIRI_MPLL(void)
{
 PLLCLK_CSCR.bits.FIR_SEL=0;
 return;
}


//SPLL_External
 void
pllclk_SPLL_26M(void)
{
 PLLCLK_CSCR.bits.SP_SEL=1;
 return;
}


//SPLL_Internal
 void
pllclk_SPLL_32K(void)
{
 PLLCLK_CSCR.bits.SP_SEL=0;
 return;
}


//MPLL_External
 void
pllclk_MPLL_26M(void)
{
 PLLCLK_CSCR.bits.MCU_SEL=1;
 return;
}


//MPLL_Internal
 void
pllclk_MPLL_32K(void)
{
 PLLCLK_CSCR.bits.MCU_SEL=0;
 return;
}


//BCLK_Divider
 void
pllclk_BCLK_Divider(uint32_t BCLKDIV)
{
 PLLCLK_CSCR.bits.BCLKDIV=BCLKDIV;
 return;
}


//PERCLK_Divider
 void
pllclk_PERCLK_Divider(uint32_t IPDIV)
{
 PLLCLK_CSCR.bits.IPDIV=IPDIV;
 return;
}


//OSC26M_Divider
 void
pllclk_OSC26M_Divider(uint32_t OSC26M_DIV1P5)
{
 PLLCLK_CSCR.bits.OSC26M_DIV1P5=OSC26M_DIV1P5;
 return;
}


//OSC26M
 void
pllclk_OSC26M(uint32_t EN)
{
 PLLCLK_CSCR.bits.OSC26M_EN=EN;
 return;
}

//FPM
 void
pllclk_FPM(uint32_t EN)
{
 PLLCLK_CSCR.bits.FPM_EN=EN;
 return;
}

//SPLL
 void
pllclk_SPLL(uint32_t EN)
{
 PLLCLK_CSCR.bits.SPEN=EN;
 return;
}

//MPLL
 void
pllclk_MPLL(uint32_t EN)
{
 PLLCLK_CSCR.bits.MPEN=EN;
 return;
}


//MPLL_FrequencyOnlyLock
 void
pllclk_MPLL_FrequencyOnlyLock(void)
{
 PLLCLK_MPCTL0.bits.CPLM=0;
 return;
}


//MPLL_FrequencyPhaseLock
 void
pllclk_MPLL_FrequencyPhaseLock(void)
{
 PLLCLK_MPCTL0.bits.CPLM=1;
 return;
}


//MPLL_Predivider
 void
pllclk_MPLL_Predivider(uint32_t PD)
{
 PLLCLK_MPCTL0.bits.PD=PD;
 return;
}


//MPLL_Multiplier_Denominator
 void
pllclk_MPLL_Multiplier_Denominator(uint32_t MFD)
{
 PLLCLK_MPCTL0.bits.MFD=MFD;
 return;
}


//MPLL_Multiplier_Integer
 void
pllclk_MPLL_Multiplier_Integer(uint32_t MFI)
{
 PLLCLK_MPCTL0.bits.MFI=MFI;
 return;
}


//MPLL_Multiplier_Numerator
 void
pllclk_MPLL_Multiplier_Numerator(uint32_t MFN)
{
 PLLCLK_MPCTL0.bits.MFN=MFN;
 return;
}


//MPLL_Lock
 void
pllclk_MPLL_Lock(void)
{
 PLLCLK_MPCTL1.bits.LF=1;
 return;
}


//MPLL_Unlock
 void
pllclk_MPLL_Unlock(void)
{
 PLLCLK_MPCTL1.bits.LF=0;
 return;
}


//MPLL_BRM_FirstOrder
 void
pllclk_MPLL_BRM_FirstOrder(void)
{
 PLLCLK_MPCTL1.bits.BRMO=0;
 return;
}


//MPLL_BRM_SecondOrder
 void
pllclk_MPLL_BRM_SecondOrder(void)
{
 PLLCLK_MPCTL1.bits.BRMO=1;
 return;
}


//SPLL_FrequencyOnlyLock
 void
pllclk_SPLL_FrequencyOnlyLock(void)
{
 PLLCLK_SPCTL0.bits.CPLM=0;
 return;
}


//SPLL_FrequencyPhaseLock
 void
pllclk_SPLL_FrequencyPhaseLock(void)
{
 PLLCLK_SPCTL0.bits.CPLM=1;
 return;
}


//SPLL_Predivider
 void
pllclk_SPLL_Predivider(uint32_t PD)
{
 PLLCLK_SPCTL0.bits.PD=PD;
 return;
}


//SPLL_Multiplier_Denominator
 void
pllclk_SPLL_Multiplier_Denominator(uint32_t MFD)
{
 PLLCLK_SPCTL0.bits.MFD=MFD;
 return;
}


//SPLL_Multiplier_Integer
 void
pllclk_SPLL_Multiplier_Integer(uint32_t MFI)
{
 PLLCLK_SPCTL0.bits.MFI=MFI;
 return;
}


//SPLL_Multiplier_Numerator
 void
pllclk_SPLL_Multiplier_Numerator(uint32_t MFN)
{
 PLLCLK_SPCTL0.bits.MFD=MFN;
 return;
}