mx21_lcd.c

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division:  WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name:        MX21_LCD.c
*     Revision Number:  0.1
*     Author(s):        E Kroitor
*     Date created:     30 Sept 2004
*     Revision History:
*
*        Date      Rev     Description
*        ----      ---     -----------
*       30Sept04   0.1     First draft
*
**********************************************************************/

#include "MX21_LCD.h"


// Set up LCD panel to display a preloaded image 
// (image should be loaded in address IMAGE_ADDRESS) 

void 
lcdSetup()
{
 
 SYSCTRL_DSCR1.all = 0x00000000; // Drive strength
 
    // Peripheral Clock Divider Register
   	PLLCLK_PCDR1.bits.PERDIV3 = 7; // PERDIV3 is the divider for LCD
	                                     

    // LCD OFF by bit 9 Memory Map IO Register
    *(p_uint16_t) 0xCC800000 = 0x0000;

	
     // Disable LCD controller
	PLLCLK_PCCR0.bits.PERCLK3_EN =0;
	PLLCLK_PCCR0.bits.HCLK_LCDC_EN =0;

    // Clock and GPIO setup   
	GPIO_PTA_GIUS.all = 0;   // Use Multiplex function      
    GPIO_PTA_GPR.all = 0;    // Select primary function
    

    // LCD Panel     
	LCDC_LSSAR.all = IMAGE_ADDRESS;   // Screen Start Address of LCD Panel  
									  // holds pixel data for a new frame 
									  // from the SSA address.
   
	
	LCDC_LSR.bits.XMAX = (LCD_WIDTH / 16); // Holds screen X Axis 
	LCDC_LSR.bits.YMAX = LCD_HEIGHT;	   // Specifies the Height of 
	                                       // the LCD panel										
				   
  	LCDC_LVPWR.all = IMAGE_WIDTH * IMAGE_BPP / 32; 

  		
    // Cursors Controls   
    LCDC_LCPR.bits.CC = 0;		// Cursor control 
    LCDC_LCPR.bits.OP = 0;		// Arithmetic operator Control
	LCDC_LCPR.bits.CXP = 0;	    // Cursor X position	 
    LCDC_LCPR.bits.CYP = 0;     // Cursor Y Position 
  		 				
  	LCDC_LCCMR.all = 0;
  		 

    // Panel Control register      	 
	LCDC_LPCR.bits.TFT = 1;	    	// TFT enable
	LCDC_LPCR.bits.COLOR = 1;		// Color enable (set for TFT)
	LCDC_LPCR.bits.PBSIZ = 3;		// Panel Bus Width, 0=1 bit,1=2,2=4,3=8 (does not matter for TFT)
	LCDC_LPCR.bits.BPIX = 5;		// BPP, 0=1bpp,1=2,2=4,3=8,4=12,5=16
	LCDC_LPCR.bits.PIXPOL = 1;		// Pixel Polarity, 0 = Active High, 1 = Active Low
	LCDC_LPCR.bits.FLMPOL = 0;		// First Line Marker Polarity, "
	LCDC_LPCR.bits.LPPOL = 0;		// Line Pulse Polarity, "
    LCDC_LPCR.bits.CLKPOL = 0;		// LCD Shift Clock, 0 = Active Falling, 1 = Active Rising (reverse for TFT)
    LCDC_LPCR.bits.OEPOL = 1;		// Output Enable Polarity, 0= Active High, 1 = Active Low
    LCDC_LPCR.bits.SCLKIDLE = 0;	// LSCLK Idle Enable (when VSYNC is idle in TFT mode)
    LCDC_LPCR.bits.END_SEL = 1; 	// Endian Select, 0 = Little, 1 = Big
    LCDC_LPCR.bits.SWAP_SEL = 0;	// Swap Select, 0 = 16bpp, 1 = else
    LCDC_LPCR.bits.REV_VS = 0;		// Reverse Vertical Scan
    LCDC_LPCR.bits.ACDSEL = 1;		// ACD Clock Source select
    LCDC_LPCR.bits.ACD = 11;		// ACD Stuff
    LCDC_LPCR.bits.SCLKSEL = 1;	    // LSCLK Select, 0 = Disable OE & LSCLK when no data output in TFT mode for power savings, 1 = Always on
    LCDC_LPCR.bits.SHARP = 1; 		// Sharp Panel Signals Enable
    LCDC_LPCR.bits.PCD = 7; 		// Pixel CLK Divider, actual divider is PCD value + 1 

    // Horizontal configuration register	  			
   	LCDC_LHCR.bits.H_WAIT_2 = 6;	// H_WAIT2 + 3 = delay between HSYNC & first data of next line       
  	LCDC_LHCR.bits.H_WAIT_1 = 15;   // H_WAIT1 + 1 = delay in Pixel CLK periods between OE & HSYNC       
  	LCDC_LHCR.bits.H_WIDTH = 1; 	// H_WIDTH + 1 = width of Horizontal Sync Pulse in Pixel CLK periods 
  	  

    // Vertical configuration register 	     
	LCDC_LVCR.bits.V_WIDTH  = 1;	// V_WIDTH = Vertical Sync pulse width in HSYNC periods		                 
	LCDC_LVCR.bits.V_WAIT_1 = 9;	// V_WAIT1 = delay between OE and VSYNC (in TFT)                             
   	LCDC_LVCR.bits.V_WAIT_2 = 7;	// V_WAIT2 = delay between VSYNC and OE of the first line of next frame  
    
  	 
    // Panning offset register 	   	
  	LCDC_LPOR.all	= 0;
  
  
    // Sharp configuration register  	 
    
    // PS_RISE_DELAY = delay between falling edge of CLS 
    // and rising edge of PS in PERCLK2 periods
 	LCDC_LSCR.bits.PS_RISE_DELAY = 0;		
 	
 	// CLS_RISE_DELAY + 1 = delay of rising edge of CLS 
 	// to last data out from previous line in PERCLK2
 	LCDC_LSCR.bits.CLS_RISE_DELAY = 18; 	
 	
 	// REV_TOGGLE_DELAY + 1 = delay between last data out of 
 	// previous line and transition of REV in PERCLK2
  	LCDC_LSCR.bits.REV_TOGGLE_DELAY = 3;	
  	
  	// Default Grey Scale 2 settings, not relevant to TFT
  	LCDC_LSCR.bits.GRAY_2 = 0;			
  	
  	// Default Grey Scale 1 settings, not relevant to TFT
  	LCDC_LSCR.bits.GRAY_1 = 0;	
  	  
  
    // PWM contrast control register    
    
    // CLS_HI_WIDTH + 1 = width of high CLS 
    // pulse in Pixel Clock periods      
    LCDC_LPCCR.bits.CLS_HI_WIDTH = 169; 
    
    // LD Mask - Enables/Disables LD[15:0] output 
    // to zero for Sharp TFT power off sequence 
  	LCDC_LPCCR.bits.LDMSK = 0;
  	
  	// Source Select for PWM counter, 0 = Line pulse, 
  	// 1 = Pixel Clock, 2 = LCD Clock (perclk2) 
  	LCDC_LPCCR.bits.SCR = 1;
  	
  	// Contrast Control Enable 
  	LCDC_LPCCR.bits.CC_EN = 1;	

	// Pulse Width of PWM controling contrast 
  	LCDC_LPCCR.bits.PW = 255;
  	  
  	   
    // DMA control register     
    
    // Burst Length, 0 = Dynamic, 1 = Fixed  
    LCDC_LDCR.bits.BURST = 0;	
    // DMA High Mark, for fixed this is 
    // the length of the burst,  	
  	LCDC_LDCR.bits.HM = 2; 		
  	
  	// for dynamic the buffer is filled until the 
  	// number of empty words is equal to the High Mark 
  	// minus two DMA Trigger Mark, when the number of 
  	// words of data left in the buffer reach is this, 
  	// new data is burst to fill it 
  	LCDC_LDCR.bits.TM = 8; 		
  							  
    // Enable LCD Clocks and LCD panel
	PLLCLK_PCCR0.bits.PERCLK3_EN =1;
	PLLCLK_PCCR0.bits.HCLK_LCDC_EN =1;

	*(p_uint16_t) 0xCC800000 = 0x0200;  
	
    // Scrolls image on the LCD panel (if it is larger than the LCD 
    // resolution). The ADS has an LCD panel that is 320x240 (QVGA). 
    // If using the same LCD panel for a larger image then the scroll 
    // function will allow the larger image to display on the QVGA 
    // panel (scrolling across the LCD panel). If using a 320x240 image, 
    // the scroll function is not needed. Make sure the larger image size 
    // is defined on the header file under IMAGE_WIDTH and IMAGE_HEIGTH

#ifdef NOT_QVGA

while(1)
  {
	scroll(0,0,IMAGE_WIDTH-LCD_WIDTH,0,SPEED);
	scroll(IMAGE_WIDTH-LCD_WIDTH,0,IMAGE_WIDTH-LCD_WIDTH,(IMAGE_HEIGHT-LCD_HEIGHT)/2,SPEED);
	scroll(IMAGE_WIDTH-LCD_WIDTH,(IMAGE_HEIGHT-LCD_HEIGHT)/2,0,(IMAGE_HEIGHT-LCD_HEIGHT)/2,SPEED);
	scroll(0,(IMAGE_HEIGHT-LCD_HEIGHT)/2,0,IMAGE_HEIGHT-LCD_HEIGHT,SPEED);
	scroll(0,IMAGE_HEIGHT-LCD_HEIGHT,IMAGE_WIDTH-LCD_WIDTH,IMAGE_HEIGHT-LCD_HEIGHT,SPEED);
	scroll(IMAGE_WIDTH-LCD_WIDTH,IMAGE_HEIGHT-LCD_HEIGHT,0,0,SPEED);
  } 

return;
 
}

// scrolls around the background by changing SSA with delays in between
void 
scroll(int xi, 
	   int yi, 
	   int x, 
	   int y, 
	   int delay)
 {
	int xd=1,yd=1,z;
	
	if(x<xi){xd=-1;}
	if(y<yi){yd=-1;}
	
	while((xi!=x)||(yi!=y)){
		if(xi!=x){xi+=xd;}
		if(yi!=y){yi+=yd;}		
		for(z=delay;z>=0;z-=1);
		
// points SSA to x,y coordinate of image in memory
LCDC_LSSAR.all = IMAGE_ADDRESS + ((yi * IMAGE_WIDTH + xi) * IMAGE_BPP / 8);

 }
#endif

}