mx21_example.c

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division: WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name: MX21_Example.c
*     Revision Number: 0.1
*     Author(s): Sharad Kumar
*     Date created:
*     Revision History:
*        Date      Rev     Description
*        ----      ---     -----------
*        30Sep2004  0.1     First Draft
*
**********************************************************************/

#include "MX21_Example.h"


// global counters for fast and 
// normal interrupts

extern volatile int gFastInt;
extern volatile int gNormInt;



void
main(void)
{
	// initialize global counter
	// for fast and normal interrupts
	gFastInt = 0;
	gNormInt = 0;

	// config the PLL
	configPLL();			
	
	// configure the ARM platform
	configMAX();
	configAIPI();
	configAITC();
	configArm();
	
	
	// example for AITC interrupts.  this
	// example forces all 64 AITC interrupts
	// using software.
	
	testInterrupts();
		
	// example for RTC.  In this
	// example  one RTC interrupt
	// is generated.  Also uses the
	// the GPT3 for a delay value
	
	rtc_demo();

	// example for testing the UART2 in 
	// a TX, RX loop mode	
	
	uart2_Demo();
	
    // an example how to use the DMAC for 
    // memory to memory transfer
	
	dmaDemo();

   // the lcd will display an image if the IMAGE_ADDRESS 
   // memory location is pre-loaded with that image. 
   // If no image is loaded prior to running the 
   // lcd function, then only lines are visible on the 
   // lcd display
	
	lcdSetup();

	printf("\n All tests run to completion");
	return;
}




// MAX configuration may not generally be required 
// as the reset state might be suitable for many 
// application. But, here's an example of how to use the
// MAX init code routines.

void
configMAX (void) 
{

	// configure the MAX master priority for a slave.  
	// priority is established in descending order
	// in the array defined below. same master priority 
	// is used for all slaves.
	max_masters gmaster_priority[] = 
	{ MAX_MASTER5, MAX_MASTER4, MAX_MASTER3, MAX_MASTER2,
	  MAX_MASTER1, MAX_MASTER0 };

	// configure the MAX alternate master priority for a slave.
	// priority is established based in descending order
	// in the array defined below.  same master priority
	// is used for all slaves.
	max_masters galt_master_priority[] =
	{ MAX_MASTER5, MAX_MASTER4, MAX_MASTER3, MAX_MASTER2,
	  MAX_MASTER1, MAX_MASTER0 };

	// configure the slave control vector for 
	// all the masters
	uint32_t gslave_control_vec[] =
	{ gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, 
	  gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC };


	// configure the alternate slave control
	// vector for all the masters
	uint32_t galt_slave_control_vec[] =
	{ gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, 
	  gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC, gMAX_SLV_CNTR_VEC };
	
	// configure MAX arbitration mode for each of the 
	// the masters in ascending order
	max_arb_modes gmaster_arb_modes[] =
	{MAX_ARB_8, MAX_ARB_8, MAX_ARB_8, MAX_ARB_8};

	// setup MAX
 	MAX_Configure(gmaster_priority,
    	          galt_master_priority,
        	      gslave_control_vec,
            	  galt_slave_control_vec,
              	  gmaster_arb_modes);
              	  
	printf("\n MAX configured ");

	return;              	  
	
}

// This sample code is used to configure the AIPI to the known 
// reset state. It can be easily modified to change the AIPI 
// configuration and serves as an example on how to use the 
// AIPI init code routines
void
configAIPI(void) 
{
	
	// setup the AIPI

	// configure the AIPI1 and AIPI2 PAR registers

	AIPI1_WritePAR(gAIPI1_PAR);
	AIPI2_WritePAR(gAIPI2_PAR);

	// setup the peripheral size registers.
	// (usually needs to be done only once)

	// To change the configuration of a 
	// single peripheral use the functions:
	// AIPI[1,2]_ConfigPeripheral(...)
	// and specify the name of the peripheral
	// in the function argument.
	
	AIPI1_ConfigAll();
	AIPI2_ConfigAll();
	
	printf("\n AIPI configured ");
	return;
}

// This sample code is used to configure the AITC and setup the
// the 64 interrupts as either of type IRQ or FIQ with a rolling
// priority level. It also enables all the interrupts by 
// writing to the AITC_INTENNUM register.

void
configAITC(void) 
{
	
	// local variables    
    uint32_t     _intNumber;
    uint32_t     _priority;

	// Disable ARM IRQ and FIQ generation
	// until AITC is properly setup
    ARM_DisableIRQ();
    ARM_DisableFIQ();


	// configure IRQ interrupt(s)
	for(_intNumber = 0; _intNumber < gNUMBER_IRQ_INTERRUPTS; 
	    _intNumber++) 
    {
	
		// setup priority of interrupt sources
		_priority = _intNumber % AITC_MAX_INT_PRIORITY;
		AITC_SetupIRQ(_intNumber, _priority);
	}
	
	
	// configure FIQ interrupt(s)
	for(_intNumber = gNUMBER_IRQ_INTERRUPTS; 
	    _intNumber < AITC_INTERRUPT_SOURCES; _intNumber ++) {
	
		// setup priority of interrupt sources
		_priority = _intNumber % AITC_MAX_INT_PRIORITY;
		AITC_SetupFIQ(_intNumber, _priority);
	}


	// Enable ARM core interrupts by
	// writing the IRQ and FIQ bits in the CPSR
	 ARM_EnableIRQ();
	 ARM_EnableFIQ();
	
	printf("\n AITC configured for all 64 interrupts");
	return;	
}


// this configuration sets up the ARM core with the MMU and the
// instruction and data cache's enabled.  Note that (i) the
// data cache can be enabled only after the MMU has been enabled,
// (ii) the page tables must be setup for the MMU to be enabled.


void
configArm() 
{
		
	// setup the MMU
	
	// MMU Table Initialization
	ARM_MMUInit((p_uint32_t) ARM_MMUTableSetUp()); 

	// enable I cache
	ARM_ICacheEnable();

	// enable MMU
	ARM_MMUEnable();

	// enable D cache
	ARM_DCacheEnable();
	
	printf("\n ARM MMU, I cache and D cache enabled");
	
	return;	
}

// configure the PLL for operation at:
// FCLK = 266 MHz, BCLK = 88 MHz
// PERCLK1=PERCLK2=PERCLK = 44MHz
void
configPLL()
{
	 
	// PLLCLK_CSCR.all   = 0x17000E07;
	// FCLK = 266MHz, HCLK = 88 MHz
	PLLCLK_CSCR.bits.PRESC   = 0x0;
	PLLCLK_CSCR.bits.BCLKDIV = 0x3;
	
	// PLLCLK_MPCTL0.all = 0x000F2002;
	// configure MPCTL for 266 MHz
	PLLCLK_MPCTL0.bits.MFD = 0xF;
	PLLCLK_MPCTL0.bits.MFI = 0x8;
	PLLCLK_MPCTL0.bits.MFN = 0x2;
	
	// PLLCLK_SPCTL0.all = 0x807F2065;
	// configure SPCTL for  288 MHz
	PLLCLK_SPCTL0.bits.MFD = 0x7F;
	PLLCLK_SPCTL0.bits.MFI = 0x8;
	PLLCLK_SPCTL0.bits.MFN = 0x65;
	
	// restart the MPCTL and SPCTL
	// after changing the operating
	// frequency
	PLLCLK_CSCR.bits.MPLL_RESTART   = Enable;		
	PLLCLK_CSCR.bits.SPLL_RESTART   = Enable;		
	
	
	// configure PCDR0, this is left at
	// the default value
	PLLCLK_PCDR0.all = 0x64193007;
	

    // configure PCDR1
	
	PLLCLK_PCDR1.bits.PERDIV1 = 0x2;
	PLLCLK_PCDR1.bits.PERDIV2 = 0x2;
	
	
	// configure peripheral enables for PCCR0 
	PLLCLK_PCCR0.all = 0x776C680F;
	
	// configure peripheral enables for PCCR0 
	PLLCLK_PCCR1.all = 0x3E000000;
	
	printf("\n PLL configured");
	
}

// in this test all the 64 interrupts are forced one by one 
// through software. The IRQ and FIQ ISRs increment the global
// counters gFastInt and gNormInt by 1 each time an interrupt
// occurs.
// Note: this test requires ConfigAITC call to configure

void
testInterrupts() 
{

	// local variables    
    uint32_t     _intNumber;
	
	// The ISRs for both IRQ and FIQ are simplistic
	// and on each invocation increment by 1 the global 
	// counters gFastInt and gNormInt.
	printf("\n");
	printf("\n Testing all 64 Interrupts");
	printf("\n First 32 interrupts configured as Normal Interrupts,");
	printf("\n next 32 interrupts configured as Fast Interrupts");
	
	// First force all of the normal interrupts one by one");
	
	if ((0 != gFastInt) && (0 != gNormInt)) 
	{
		printf(" The interrupt test case FAILS\n");	
		PRINTF(" The value of the gNormInt, gFastInt are %d, %d\n", 
		        gNormInt, gFastInt);

		return;
	}

	// force all normal interrupts
	for (_intNumber = 0;_intNumber < gNUMBER_IRQ_INTERRUPTS;_intNumber++)
	{
		AITC_ForceOneInt(_intNumber);			
		softDelay(gDELAY);
	}
	
	if ((0 != gFastInt) && (gNUMBER_IRQ_INTERRUPTS != gNormInt)) 
	{
		printf(" The interrupt test case FAILS\n");	
		PRINTF(" The value of the gNormInt, gFastInt are %d, %d\n", 
		        gNormInt, gFastInt);

		return;
	}

	
	// Next force all the fast interrupts one by one
	for(_intNumber = gNUMBER_IRQ_INTERRUPTS; 
	    _intNumber < AITC_INTERRUPT_SOURCES; _intNumber ++) 
	{
		AITC_ForceOneInt(_intNumber);		
		softDelay(gDELAY);
	}
	
	if (((AITC_INTERRUPT_SOURCES - gNUMBER_IRQ_INTERRUPTS) != gFastInt) 
	      && (gNUMBER_IRQ_INTERRUPTS != gNormInt)) 
	{
		printf(" The interrupt test case FAILS\n");	
		PRINTF(" The value of the gNormInt, gFastInt are %d, %d\n", 
		        gNormInt, gFastInt);

		return;
	}	
	
	printf("\n The number of gNormInt, gFastInt received were %d, %d\n", 
	        gNormInt, gFastInt);	
	        
	printf("\n The interrupt test case passes\n");	


	return;	
}