mx21_init.s

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

;;**********************************************************************
;;
;;        (C) COPYRIGHT 2004 FREESCALE, INC.
;;         ALL RIGHTS RESERVED
;;
;;
;;     Group/Division:  WMSG/MMDO
;;
;;     Description:
;;     Init file based on original
;;     version from ARM ltd.
;;
;;     Related Specifications:
;;
;;     Errata:
;;
;;     File Name:        MX21_Init.s
;;     Revision Number:  0.1
;;     Author(s):        Sharad Kumar
;;     Date created:     30Apr2004
;;     Revision History:
;;        Date      Rev     Description
;;        ----      ---     -----------
;;        30Apr04  0.1     First draft
;;
;;*********************************************************************/



; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, with IRQ and FIQ disabled.


	.section  Init
    .global   mx21_Init
;;    .global __init_user


; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR         .equ     0x10
Mode_FIQ         .equ     0x11
Mode_IRQ         .equ     0x12
Mode_SVC         .equ     0x13
Mode_ABT         .equ     0x17
Mode_UNDEF       .equ     0x1B
Mode_SYS         .equ     0x1F ; available on ARM Arch 4 and later

I_Bit            .equ     0x80 ; when I bit is set, IRQ is disabled
F_Bit            .equ     0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations
         

Len_UND_Stack    .equ     1024
Len_FIQ_Stack    .equ     1024
Len_IRQ_Stack    .equ     1024
Len_USR_Stack    .equ     1024
Len_SVC_Stack    .equ     8192

USR_Stack_Offset .equ     Len_SVC_Stack
IRQ_Stack_Offset .equ     USR_Stack_Offset  +  Len_USR_Stack
FIQ_Stack_Offset .equ     IRQ_Stack_Offset  +  Len_IRQ_Stack
UND_Stack_Offset .equ     FIQ_Stack_Offset  +  Len_FIQ_Stack
ABT_Stack_Offset .equ     UND_Stack_Offset  +  Len_UND_Stack

        .public __SP_INIT

;;__init_user:
mx21_Init:

; --- Initialise stack pointer registers
; Enter SVC mode and set up the SVC stack pointer
        MSR     CPSR_c, #Mode_SVC | I_Bit | F_Bit ; No interrupts 
        LDR     SP, @SVC_Stack

; Enter IRQ mode and set up the IRQ stack pointer
        MSR     CPSR_c, #Mode_IRQ | I_Bit | F_Bit ; No interrupts
        LDR     SP, @IRQ_Stack

; Enter FIQ mode and set up the FIQ stack pointer
        MSR     CPSR_c, #Mode_FIQ | I_Bit | F_Bit ; No interrupts
        LDR     SP, @FIQ_Stack

; Enter USR mode and set up the USR stack pointer
        MSR     CPSR_c, #Mode_IRQ | I_Bit | F_Bit ; No interrupts
        LDR     SP, @IRQ_Stack

; Finally, Re-Enter SVC mode
        MSR     CPSR_c, #Mode_SVC | I_Bit | F_Bit ; No interrupts
        LDR     SP, @SVC_Stack

		MOV     PC, LR


@SVC_Stack  
 .long    __SP_INIT                       ; SVC stack at top of memory

@USR_Stack       
 .long     __SP_INIT -  USR_Stack_Offset  ; followed by USR Stack

@IRQ_Stack       
 .long     __SP_INIT - IRQ_Stack_Offset   ; followed by IRQ stack

@FIQ_Stack		
 .long     __SP_INIT - FIQ_Stack_Offset   ; followed by FIQ stack

@ABT_Stack       
 .long     __SP_INIT - UND_Stack_Offset   ; followed by ABT stack

@UND_Stack       
 .long     __SP_INIT - ABT_Stack_Offset   ; followed by UND stack