mx21_init.s.list

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

                             ;;**********************************************************************
                             ;;
                             ;;        (C) COPYRIGHT 2004 FREESCALE, INC.
                             ;;         ALL RIGHTS RESERVED
                             ;;
                             ;;     THIS IS PROPRIETARY SOURCE CODE OF FREESCALE, INC.
                             ;;     The copyright notice above does not evidence any actual or
                             ;;     intended publication of such source code
                             ;;
                             ;;     Freescale Confidential Proprietary
                             ;;
                             ;;
                             ;;     Group/Division:  WMSG/MMDO
                             ;;
                             ;;     Description:
                             ;;     Init file based on original
                             ;;     version from ARM ltd.
                             ;;
                             ;;     Related Specifications:
                             ;;
                             ;;     Errata:
                             ;;
                             ;;     File Name:        MX21_Init.s
                             ;;     Revision Number:  0.1
                             ;;     Author(s):        Sharad Kumar
                             ;;     Date created:     30Apr2004
                             ;;     Revision History:
                             ;;        Date      Rev     Description
                             ;;        ----      ---     -----------
                             ;;        30Apr04  0.1     First draft
                             ;;
                             ;;*********************************************************************/
                             ; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, with IRQ and FIQ disabled.
                                                .section     Init             
                                                .global      mx21_Init        
                             ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
0x00000010:                  Mode_USR           .equ         0x10             
0x00000011:                  Mode_FIQ           .equ         0x11             
0x00000012:                  Mode_IRQ           .equ         0x12             
0x00000013:                  Mode_SVC           .equ         0x13             
0x00000017:                  Mode_ABT           .equ         0x17             
0x0000001b:                  Mode_UNDEF         .equ         0x1B             
0x0000001f:                  Mode_SYS           .equ         0x1F             ; available on ARM Arch 4 and later
0x00000080:                  I_Bit              .equ         0x80             ; when I bit is set, IRQ is disabled
0x00000040:                  F_Bit              .equ         0x40             ; when F bit is set, FIQ is disabled
                             ; --- System memory locations

0x00000400:                  Len_UND_Stack      .equ         1024             
0x00000400:                  Len_FIQ_Stack      .equ         1024             
0x00000400:                  Len_IRQ_Stack      .equ         1024             
0x00000400:                  Len_USR_Stack      .equ         1024             
0x00002000:                  Len_SVC_Stack      .equ         8192             
0x00002000:                  USR_Stack_Offset   .equ         Len_SVC_Stack    
0x00002400:                  IRQ_Stack_Offset   .equ         USR_Stack_Offset  +  Len_USR_Stack 
0x00002800:                  FIQ_Stack_Offset   .equ         IRQ_Stack_Offset  +  Len_IRQ_Stack 
0x00002c00:                  UND_Stack_Offset   .equ         FIQ_Stack_Offset  +  Len_FIQ_Stack 
0x00003000:                  ABT_Stack_Offset   .equ         UND_Stack_Offset  +  Len_UND_Stack 
                                                .public      __SP_INIT        
                             mx21_Init                                        
                             ; --- Initialise stack pointer registers
                             ; Enter SVC mode and set up the SVC stack pointer
0x00000000: d3f021e3                            msr          CPSR_c, #Mode_SVC | I_Bit | F_Bit ; No interrupts
0x00000004: 20d09fe5                            ldr          SP, @SVC_Stack   
                             ; Enter IRQ mode and set up the IRQ stack pointer
0x00000008: d2f021e3                            msr          CPSR_c, #Mode_IRQ | I_Bit | F_Bit ; No interrupts
0x0000000c: 20d09fe5                            ldr          SP, @IRQ_Stack   
                             ; Enter FIQ mode and set up the FIQ stack pointer
0x00000010: d1f021e3                            msr          CPSR_c, #Mode_FIQ | I_Bit | F_Bit ; No interrupts
0x00000014: 1cd09fe5                            ldr          SP, @FIQ_Stack   
                             ; Enter USR mode and set up the IRQ stack pointer
0x00000018: d2f021e3                            msr          CPSR_c, #Mode_IRQ | I_Bit | F_Bit ; No interrupts
0x0000001c: 10d09fe5                            ldr          SP, @IRQ_Stack   
                             ; Finally, Re-Enter SVC mode
0x00000020: d3f021e3                            msr          CPSR_c, #Mode_SVC | I_Bit | F_Bit ; No interrupts
0x00000024: 00d09fe5                            ldr          SP, @SVC_Stack   
0x00000028: 0ef0a0e1                            mov          PC, LR           
                             @SVC_Stack                                       
0x0000002c: 00000000                            .long        __SP_INIT        ; SVC stack at top of memory
                             @USR_Stack                                       
0x00000030: 00000000                            .long        __SP_INIT -  USR_Stack_Offset ; followed by USR Stack
                             @IRQ_Stack                                       
0x00000034: 00000000                            .long        __SP_INIT - IRQ_Stack_Offset ; followed by IRQ stack
                             @FIQ_Stack                                       
0x00000038: 00000000                            .long        __SP_INIT - FIQ_Stack_Offset ; followed by FIQ stack
                             @ABT_Stack                                       
0x0000003c: 00000000                            .long        __SP_INIT - UND_Stack_Offset ; followed by ABT stack
                             @UND_Stack                                       
0x00000040: 00000000                            .long        __SP_INIT - ABT_Stack_Offset ; followed by UND stack

                             .end