mx21_uart2.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

// Asynchronous IR WAKE Interrupt Flag--Indicates
//  that the IR WAKE pulse was detected (on the RXD
//  pin). Clear AIRINT by writing 1 to it. Writing
//  0 to AIRINT has no effect.
// Returns:
//	  0 = No pulse was detected on the RXD pin
//	  1 = A pulse was detected on the RXD pin
//-------------------------------------------------*/
 uint32_t
uart2_IR_AsyncWakeFlag(void);


/*---------------------------------------------------
// AWAKE, USR1[4]
// Function automatically clears bit if set.
// Asynchronous WAKE Interrupt Flag--Indicates that
//  a falling edge was detected on the RXD pin.
//  Clear AWAKE by writing 1 to it. Writing 0 to
//  AWAKE has no effect.
// Returns:
//	  0 = No falling edge was detected on the
//	   RXD pin
//	  1 = A falling edge was detected on the
//	   RXD pin
//-------------------------------------------------*/
 uint32_t
uart2_AsyncWakeFlag(void);


/*---------------------------------------------------
// ADET, USR2[15]
// Function automatically clears bit if set.
//  Automatic Baud Rate Detect Complete --Indicates
//  that an 'A' or 'a was received and that the
//  receiver detected and verified the incoming baud
//  rate. Clear ADET by writing 1 to it. Writing 0
//  to ADET has no effect.
// Returns:
//	  0 = ASCII 'A' or 'a' was not received
//	  1 = ASCII 'A' or 'a' was received (write 1
//     to clear)
//-------------------------------------------------*/
 uint32_t
uart2_AutoBaudCompleteFlag(void);//


/*---------------------------------------------------
// TXFE, USR2[14]
//  Transmit Buffer FIFO Empty --Indicates that the
//  transmit buffer (TxFIFO) is empty. TXFE is
//  cleared automatically when data is written to
//  the TxFIFO. Even though TXFE is high, the
//  transmission might still be in progress.
// Returns:
//	0 = The transmit buffer (TxFIFO) is not
//	 empty
//	1 = The transmit buffer (TxFIFO) is empty
//-------------------------------------------------*/
 uint32_t
uart2_TxFIFO_EmptyFlag(void);//


/*---------------------------------------------------
// IDLE, USR2[12]
// Function automatically clears bit if set.
//  Idle Condition --Indicates that an idle
//  condition has existed for more than a
//  programmed amount frame (see ). The interrupt
//  generated by this IDLE bit is cleared by
//  writing 1 to IDLE. Writing 0 to IDLE has no
//  effect.
// Returns:
//	  0 = No idle condition detected
//	  1 = Idle condition detected (write 1 to
//	   clear)
//-------------------------------------------------*/
 uint32_t
uart2_RxIdleDetectFlag(void);//


/*---------------------------------------------------
// ACST, USR2[11]
// Function automatically clears bit if set.
//  Autobaud Counter Stopped --In autobaud
//  detection (ADBR=1), indicates the counter which
//  determines the baudrate was running and is now
//  stopped. This means either START bit is
//  finished (if ADNIMP=1), or Bit0 is finished (if
//  ADNIMP=0). See 36.5.10.2 for more details. An
//  interrupt can be flagged if ACIEN=1.
// Returns:
//	  0 = Measurement of bit length not
//	   finished (in autobaud)
//	  1 = Measurement of bit length finished
//	   (in autobaud). (write a 1 to clear)
//-------------------------------------------------*/
 uint32_t
uart2_AutoBaudCounterStoppedFlag(void);//


/*---------------------------------------------------
// IRINT, USR2[8]
// Function automatically clears bit if set.
//  Serial Infrared Interrupt Flag --When an edge
//  is detected on the RX pin during SIR Mode, this
//  flag will be asserted. This flag can cause an
//  interrupt which can be masked using the control
//  bit ENIRI: UCR4 [8].
// Returns:
//	  0 = no edge detected
//	  1 = valid edge detected (write a 1 to
//	   clear)
//-------------------------------------------------*/
 uint32_t
uart2_IR_Flag(void);


/*---------------------------------------------------
// WAKE, USR2[7]
// Function automatically clears bit if set.
//  Wake --Indicates the start bit is detected.
//  WAKE can generate an interrupt that can be
//  masked using the WKEN bit. Clear WAKE by
//  writing 1 to it. Writing 0 to WAKE has no
//  effect.
// Returns:
//	  0 = start bit not detected
//	  1 = start bit detected (write 1 to clear)
//-------------------------------------------------*/
 uint32_t
uart2_WakeFlag(void);


/*---------------------------------------------------
// RTSF, USR2[4]
// Function automatically clears bit if set.
//  RTS Edge Triggered Interrupt Flag --Indicates
//  if a programmed edge is detected on the RTS
//  pin. The RTEC bits select the edge that
//  generates an interrupt (see ). RTSF can
//  generate an interrupt that can be masked using
//  the RTSEN bit. Clear RTSF by writing 1 to it.
//  Writing 0 to RTSF has no effect.
// Returns:
//	  0 = Programmed edge not detected on RTS
//	  1 = Programmed edge detected on RTS
//	   (write 1 to clear)
//-------------------------------------------------*/
 uint32_t
uart2_RTS_EdgeFlag(void);//


/*---------------------------------------------------
// TXDC, USR2[3]
//  Transmitter Complete --Indicates that the
//  transmit buffer (TxFIFO) and Shift Register is
//  empty; therefore the transmission is complete.
//  TXDC is cleared automatically when data is
//  written to the TxFIFO.
// Returns:
//	0 = Transmit is incomplete
//	1 = Transmit is complete
//-------------------------------------------------*/
 uint32_t
uart2_TxComplete(void);//


/*---------------------------------------------------
// BRCD, USR2[2]
// Function automatically clears bit if set.
//  BREAK Condition Detected --Indicates that a
//  BREAK condition was detected by the receiver.
//  Clear BRCD by writing 1 to it. Writing 0 to
//  BRCD has no effect.
// Returns:
//	  0 = No BREAK condition was detected
//	  1 = A BREAK condition was detected (write
//	   1 to clear)
//-------------------------------------------------*/
 uint32_t
uart2_RxBreakDetectFlag(void);//


/*---------------------------------------------------
// ORE, USR2[1]
// Function automatically clears bit if set.
//  Overrun Error --Indicates that the receive
//  buffer (RxFIFO) was full when data was being
//  received. Clear ORE by writing 1 to it. Writing
//  0 to ORE has no effect.
// Returns:
//	  0 = No overrun error
//	  1 = Overrun error (write 1 to clear)
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_OverrunErrorFlag(void);//


/*---------------------------------------------------
// RDR, USR2[0]
//  Receive Data Ready --Indicates that at least 1
//  character is received and written to the
//  RxFIFO. If the URXD_x register is read and
//  there is only 1 character in the RxFIFO, RDR is
//  automatically cleared.
// Returns:
//	0 = No receive data ready
//	1 = Receive data ready
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_Ready(void);//


/*---------------------------------------------------
// ESC_CHAR, UESC[7-0]
//  UART Escape Character --Holds the selected
//  escape character that all received characters
//  are compared against to detect an escape
//  sequence.
//-------------------------------------------------*/
 void
uart2_RxEscapeCharacter(uint32_t);//


/*---------------------------------------------------
// TIM, UTIM[11-0]
//  UART Escape Timer --Holds the maximum interval
//  allowed between escape characters.
//-------------------------------------------------*/
 void
uart2_RxEscapeTimer(uint32_t);//


/*---------------------------------------------------
// INC, UBIR[15-0]
// Incremental Numerator--Holds the numerator value
//  minus one of the BRM ratio (see ). The UBIR
//  register MUST be updated before the UBMR
//  register for the baud rate to be updated
//  correctly. If only one register is written to
//  by software, the BRM will ignore this data
//  until the other register is written to by
//  software. Updating this field using byte
//  accesses is not recommended and is undefined.
//  UARTx_EN (PCCR0[3:0]) MUST be enabled before
//  accessing this register.
//-------------------------------------------------*/
 void
uart2_BRMNumerator(uint32_t);//


/*---------------------------------------------------
// MOD, UBMR[15-0]
//  Modulator Denominator --Holds the value of the
//  denominator minus one of the BRM ratio (see ).
//  The UBIR register MUST be updated before the
//  UBMR register for the baud rate to be updated
//  correctly. If only one register is written to
//  by software, the BRM will ignore this data
//  until the other register is written to by
//  software. Updating this register using byte
//  accesses is not recommended and undefined.
//  UARTx_EN (PCCR0[3:0]) MUST be enabled before
//  accessing this register.
//-------------------------------------------------*/
 void
uart2_BRMDenominator(uint32_t);


/*---------------------------------------------------
// FIX ME
// BCNT, UBRC[15-0]
//  Baud Rate Count Register --This read only
//  register is used to count the start bit of the
//  incoming baud rate (if ADNIMP=1), or start bit
//  + bit0 (if ADNIMP=0). When the measurement is
//  done, the Baud Rate Count Register contains the
//  number of UART internal clock cycles (clock
//  after divider) present in an incoming bit. BCNT
//  retains its value until the next Automatic Baud
//  Rate Detection sequence has been initiated. The
//  16-bit Baud Rate Count register is reset to 4
//  and stays at hex FFFF in the case of an
//  overflow.
//-------------------------------------------------*/
 uint32_t
uart2_AutoBaudCounter(void);//


/*---------------------------------------------------
// ONEMS, ONEMS[15-0]
//  One Millisecond Register --This 16-bit register
//  must contain the value of the UART internal
//  frequency divided by 1000. The internal
//  frequency is obtained after the UART internal
//  divider. In fact this register contains the
//  value corresponding to the number of UART
//  internal clock cycles are present in one
//  millisecond.
//-------------------------------------------------*/
 void
uart2_InternalKHz(uint32_t);//


/*---------------------------------------------------
// TXEMPTY, UTS[6]
// Tx FIFO Empty--Indicates that the TxFIFO is
//  empty.
// Returns:
//	0 = The Tx FIFO is not empty
//	1 = The Tx FIFO is empty
//-------------------------------------------------*/
 uint32_t
uart2_TxFIFO_Empty(void);//


/*---------------------------------------------------
// RXEMPTY, UTS[5]
// Rx FIFO Empty--Indicates the RxFIFO is empty.
// Returns:
//	0 = The Rx FIFO is not empty
//	1 = The Rx FIFO is empty
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_Empty(void);//


/*---------------------------------------------------
// TXFULL, UTS[4]
// Tx FIFO Full--Indicates the TxFIFO is full.
// Returns:
//	0 = The Tx FIFO is not full
//	1 = The Tx FIFO is full
//-------------------------------------------------*/
 uint32_t
uart2_TxFIFO_Full(void);//


/*---------------------------------------------------
// RXFULL, UTS[3]
// Rx FIFO Full--Indicates the RxFIFO is full.
// Returns:
//	0 = The Rx FIFO is not full
//	1 = The Rx FIFO is full
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_Full(void);//


/*---------------------------------------------------
// SOFTRST, UTS[0]
// Software Reset--Indicates the status of the
//  software reset (SRST).
// Returns:
//	0 = No software reset
//	1 = Generate software reset
//-------------------------------------------------*/
 uint32_t
uart2_SoftResetStatus(void);//




#endif /* _MX21GPT_H_ */