mx21_uart2.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

// RXDMUXSEL, UCR3[2] = 1
//
// RXD Muxed Input Selected = Selects the
//  IPP_UART_RXD_MUX input pin for serial and 
//  infrared input signal. In i.MX21 this bit should
//  be set to 1.
//-------------------------------------------------*/
 void
uart2_RxSetMux(void);


/*---------------------------------------------------
// INVT, UCR3[1] = Enable/Disable
//   Result: Disabled for standard active low
//    transmission, Enabled for active high
//
//  Inverted Infrared Transmission --Sets the
//  active level for the transmission. When INVT is
//  cleared, the infrared logic block transmits a
//  positive IR 3/16 pulse for all 0s and 0s are
//  transmitted for 1s. When INVT is set (INVT =
//  1), the infrared logic block transmits an
//  active low or negative infrared 3/16 pulse for
//  all 0s and 1s are transmitted for 1s.
//-------------------------------------------------*/
 void
uart2_IR_TxInvert(uint32_t);


/*---------------------------------------------------
// ACIEN, UCR3[0] = Enable/Disable
//
//  Autobaud Counter Interrupt Enable --This
//  bit is used to mask the autobaud counter
//  stopped interrupt.
//-------------------------------------------------*/
 void
uart2_AutoBaudCounterStoppedInterrupt(uint32_t);//


/*---------------------------------------------------
// CTSTL, UCR4[15-10] = 000000 => 0 characters received
//			000001 => 1 characters in the RxFIFO
//                      ...
//			100000 => 32 characters in the RxFIFO
//			   (maximum) All Other Settings Reserved
//  CTS Trigger Level --Controls the threshold at
//  which the CTS pin is deasserted by the RxFIFO.
//  After the trigger level is reached and the CTS
//  pin is deasserted, the RxFIFO continues to
//  receive data until it is full. The CTSTL bits
//  are encoded as shown in the Settings column.
//-------------------------------------------------*/
 void
uart2_CTS_TriggerLevel(uint32_t);//


/*---------------------------------------------------
// INVR, UCR4[9] = Enable/Disable
//   Result: Disable results in standard Active low
//    detection, Enable in Active high
//
//  Inverted Infrared Reception --Determines
//  the logic level for the detection. When
//  cleared, the infrared logic block expects an
//  active low or negative IR 3/16 pulse for 0s and
//  1s are expected for 1s. When INVR is set (INVR
//  = 1), the infrared logic block expects an
//  active high or positive IR 3/16 pulse for 0s
//  and 0s are expected for 1s.
//-------------------------------------------------*/
 void
uart2_IR_RxInvert(uint32_t);


/*---------------------------------------------------
// ENIRI, UCR4[8] = Enable/Disable
//
//  Serial Infrared Interrupt Enable
//  --Enables/Disables the serial infrared
//  interrupt.
//-------------------------------------------------*/
 void
uart2_IR_Interrupt(uint32_t);


/*---------------------------------------------------
// WKEN, UCR4[7] = Enable/Disable
//
//  WAKE Interrupt Enable --Enables/Disables
//  the WAKE bit to generate an interrupt. The WAKE
//  bit is set at the detection of a start bit by
//  the receiver.
//-------------------------------------------------*/
 void
uart2_WakeInterrupt(uint32_t);


/*---------------------------------------------------
// IRSC, UCR4[5] = _16xBaud/_UARTRefClock 0/1
//   Result: 0 = vote logic uses the sampling clock
//    (16x baud rate) for normal operation, 1 = it
//    uses the UART reference clock
//
//  IR Special Case --Selects the clock for the
//  vote logic. When set, IRSC switches the vote
//  logic clock from the sampling clock to the UART
//  reference clock. The IR pulses are counted a
//  predetermined amount of time depending on the
//  reference frequency.
//-------------------------------------------------*/
 void
uart2_IR_SamplingClock(uint32_t);//


/*---------------------------------------------------
// TCEN, UCR4[3] = Enable/Disable
//
//  Transmit  Complete Interrupt Enable
//  --Enables/Disables the TXDC bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_TxCompleteInterrupt(uint32_t);//


/*---------------------------------------------------
// BKEN, UCR4[2] = Enable/Disable
//
//  BREAK Condition Detected Interrupt Enable
//  --Enables/Disables the BRCD bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_RxBreakDetectInterrupt(uint32_t);//


/*---------------------------------------------------
// OREN, UCR4[1] = Enable/Disable
//
//  Receiver Overrun Interrupt Enable
//  --Enables/Disables the ORE bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_RxFIFO_OverrunErrorInterrupt(uint32_t);//


/*---------------------------------------------------
// TXTL, UFCR[15-10] = 000000 => Reserved
//		       000001 => Reserved
//		       000010 => TxFIFO has 2 or fewer characters
//		       011111 => TxFIFO has 31 or fewer characters
//                     ...
//		       100000 => TxFIFO has 32 characters (maximum)
//			  All Other Settings Reserved
//  Transmitter Trigger Level --Controls the
//  threshold at which a maskable interrupt is
//  generated by the TxFIFO. A maskable interrupt
//  is generated whenever the data level in the
//  TxFIFO falls below the selected threshold. The
//  bits are encoded as shown in the Settings
//  column.
//-------------------------------------------------*/
 void
uart2_TxFIFO_TriggerLevel(uint32_t);//


/*---------------------------------------------------
// RFDIV, UFCR[9-7] = 1..7
//   Result: Divide input clock by n
//
// Reference Frequency Divider--Controls the
//  divide ratio for the reference clock. The input
//  clock is IPG_CLK. The output from the divider
//  must be synchronous with the bus clock.
//-------------------------------------------------*/
 void
uart2_ReferenceFrequencyDivider(uint32_t);//


/*---------------------------------------------------
// RXTL, UFCR[5-0] = 000000 => 0 characters received
//		     000001 => RxFIFO has 1 character
//		     011111 => RxFIFO has 31 characters
//                   ...
//		     100000 => RxFIFO has 32 characters (maximum) All
//			Other Settings Reserved
//  Receiver Trigger Level --Controls the threshold
//  at which a maskable interrupt is generated by
//  the RxFIFO. A maskable interrupt is generated
//  whenever the data level in the RxFIFO reaches
//  the selected threshold. The RXTL bits are
//  encoded as shown in the Settings column.
//-------------------------------------------------*/
 void
uart2_RxFIFO_TriggerLevel(uint32_t);//


/*---------------------------------------------------
// PARITYERR, USR1[15]
// Function automatically clears bit if set.
//  Parity Error Interrupt Flag --Indicates a
//  parity error is detected. PARITYERR is cleared
//  by writing 1 to it. Writing 0 to PARITYERR has
//  no effect. When parity is disabled, PARITYERR
//  always reads 0. At reset, PARITYERR is set to
//  0.
// Returns:
//	  0 = No parity error detected
//	  1 = Parity error detected
//-------------------------------------------------*/
 uint32_t
uart2_RxParityErrorFlag(void);//


/*---------------------------------------------------
// RTSS, USR1[14]
//  RTS Pin Status --Indicates the current status
//  of the UARTx_RTS pin. A "snapshot" of
//  the pin is taken immediately before RTSS is
//  presented to the data bus. RTSS cannot be
//  cleared because all writes to RTSS are ignored.
//  At reset, RTSS is set to 0.
// Returns:
//	0 = The UARTx_RTS pin is high (inactive)
//	1 = The UARTx_RTS pin is low (active)
//-------------------------------------------------*/
 uint32_t
uart2_RTS_Status(void);//


/*---------------------------------------------------
// TRDY, USR1[13]
//  Transmitter Ready Interrupt / DMA Flag
//  --Indicates that the TxFIFO emptied below its
//  target threshold and requires data. TRDY is
//  automatically cleared when the data level in
//  the TxFIFO goes beyond above the set threshold
//  level by TXFL bits. At reset, TRDY is set to 1.
// Returns:
//	0 = The transmitter does not require data
//	1 = The transmitter requires data
//	 (interrupt posted)
//-------------------------------------------------*/
 uint32_t
uart2_TxFIFO_Ready(void);//


/*---------------------------------------------------
// RTSD, USR1[12]
// Function automatically clears bit if set.
//  RTS Delta --Indicates whether the RTS pin
//  changed state. It (RTSD) generates a maskable
//  interrupt. When in STOP mode, only RTS
//  assertion sets RTSD and wakes the ARM9 core.
//  The current state of the UARTx_RTS pin is
//  available on the RTSS bit. Clear RTSD by
//  writing 1 to it. Writing 0 to RTSD has no
//  effect. At reset, RTSD is set to 0.
// Returns:
//	  0 = UARTx_RTS pin did not change state
//	   since last cleared
//	  1 = UARTx_RTS pin changed state (write 1
//	   to clear)
//-------------------------------------------------*/
 uint32_t
uart2_RTS_DeltaFlag(void);//


/*---------------------------------------------------
// ESCF, USR1[11]
// Function automatically clears bit if set.
//  Escape Sequence Interrupt Flag --Indicates if
//  an escape sequence was detected. ESCF is
//  asserted when the ESCEN bit is set and an
//  escape sequence is detected in the RxFIFO.
//  Clear ESCF by writing 1 to it. Writing 0 to
//  ESCF has no effect.
// Returns:
//	  0 = No escape sequence detected
//	  1 = Escape sequence detected (write 1 to
//	   clear)
//-------------------------------------------------*/
 uint32_t
uart2_RxEscapeFlag(void);//


/*---------------------------------------------------
// FRAMERR, USR1[10]
// Function automatically clears bit if set.
//  Frame Error Interrupt Flag --Indicates that a
//  frame error is detected. The interrupt
//  generated by this. Clear FRAMERR by writing 1
//  to it. Writing 0 to FRAMERR has no effect.
// Returns:
//	  0 = No frame error detected
//	  1 = Frame error detected
//-------------------------------------------------*/
 uint32_t
uart2_RxFrameErrorFlag(void);//


/*---------------------------------------------------
// RRDY, USR1[9]
//  Receiver Ready Interrupt / DMA Flag --Indicates
//  that the RxFIFO data level is above the
//  threshold set by the RXFL bits. (See the RXFL
//  bits description for setting the interrupt
//  threshold.) When asserted, RRDY generates a
//  maskable interrupt or DMA request. In
//  conjunction with the CHARRDY bit in the URXDn_1
//  or URXDn_2 register, the software can continue
//  to read the RxFIFO in an interrupt service
//  routine until the RxFIFO is empty. RRDY is
//  automatically cleared when data level in the
//  RxFIFO goes below the set threshold level. At
//  reset, RRDY is set to 0.
// Returns:
//	0 = No character ready
//	1 = Character(s) ready (interrupt posted)
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_TriggerReady(void);//


/*---------------------------------------------------
// AGTIM, USR1[8]
// Function automatically clears bit if set.
// Aging Timer Interrupt Flag--Indicates that data
//  in the RxFIFO has been idle for a time of 8
//  character lengths (where a character length
//  consists of 7 or 8 bits, depending on the
//  setting of the WS bit in UCR2, with the bit
//  time corresponding to the baud rate setting)
//  and FIFO data level is less than RxFIFO
//  threshold level (RxTL in the UFCR). Clear by
//  writing a 1 to it.
// Returns:
//	  0 = AGTIM is not active
//	  1 = AGTIM is active
//-------------------------------------------------*/
 uint32_t
uart2_AgingCharacterDetectFlag(void);


/*---------------------------------------------------
// RXDS, USR1[6]
// Receiver IDLE Interrupt Flag--Indicates that the
//  receiver state machine is in an IDLE state, the
//  next state is IDLE, and the receive pin is
//  high. RXDS is automatically cleared when a
//  character is received. RXDS is reset to high.
// Returns:
//	0 = Receive in progress
//	1 = Receiver is IDLE
//-------------------------------------------------*/
 uint32_t
uart2_RxIdleStatus(void);//


/*---------------------------------------------------
// AIRINT, USR1[5]
// Function automatically clears bit if set.