mx21_uart2.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

//-------------------------------------------------*/
 void
uart2_TxFIFO_EmptyInterrupt(uint32_t);//


/*---------------------------------------------------
// RTSDEN, UCR1[5] = Enable/Disable
//
//  RTS Delta Interrupt Enable
//  --Enables/Disables the RTSD interrupt. The
//  current status of the UARTx_RTS pin is read in
//  the RTSS bit.
//-------------------------------------------------*/
 void
uart2_RTS_DeltaInterrupt(uint32_t);//


/*---------------------------------------------------
// SNDBRK, UCR1[4] = Enable/Disable
//   Result: Start or stop sending Break characters
//
//  Send Break --Forces the transmitter to send
//  a BREAK character. The transmitter finishes
//  sending the character in progress (if any) and
//  sends BREAK characters until SNDBRK is reset.
//  Because the transmitter samples SNDBRK after
//  every bit is transmitted, it is important that
//  SNDBRK is asserted high for a sufficient period
//  of time to generate a valid BREAK. After the
//  BREAK transmission completes, the UART
//  transmits 2 mark bits. The user can continue to
//  fill the TxFIFO and any characters remaining
//  are transmitted when the BREAK is terminated.
//-------------------------------------------------*/
 void
uart2_TxBreak(uint32_t);//


/*---------------------------------------------------
// TXDMAEN, UCR1[3] = Enable/Disable
//
//  Transmitter Ready DMA Enable
//  --Enables/Disables the transmit DMA request 
//  IPD_UART_TX_DMAREQ when the transmitter has one
//  or more slots available in the TxFIFO. The fill
//  level in the TxFIFO that generates the 
//  IPD_UART_TX_DMAREQ is controlled by the TXTL
//  bits.
//-------------------------------------------------*/
 void
uart2_TxFIFO_ReadyDMA(uint32_t);//


/*---------------------------------------------------
// UARTEN, UCR1[0] = Enable/Disable
//
//  UART Enable --Enables/Disables the UART. If
//  UARTEN is negated in the middle of a
//  transmission, the transmitter stops and pulls
//  the TXD line to a logic 1. UARTEN must be set
//  to 1 before any access to UTXD and URXD
//  registers.
//-------------------------------------------------*/
 void
uart2_EN(uint32_t);//


/*---------------------------------------------------
// ESCI, UCR2[15] = Enable/Disable
//
//  Escape Sequence Interrupt Enable
//  --Enables/Disables the ESCF bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_RxEscapeInterrupt(uint32_t);//


/*---------------------------------------------------
// IRTS, UCR2[14] = Enable/Disable
//   Result: Selects whether to use UARTx_RTS Pin
//    for hardware flow control.
//
//  Ignore UARTx_RTS Pin --Forces the UARTx_RTS
//  input signal presented to the transmitter to
//  always be asserted, effectively ignoring the
//  external pin. When in this mode, the UARTx_RTS
//  pin serves as a general purpose input.
//-------------------------------------------------*/
 void
uart2_RTS_Ignore(uint32_t);//


/*---------------------------------------------------
// CTSC, UCR2[13] = Enable/Disable
//   Result: The UARTx_CTS pin is controlled by the
//    CTS bit if disabled, the RxFIFO trigger level
//    if enabled.
//
// UARTx_CTS Pin Control --Controls the
//  operation of the UARTx_CTS output pin. When
//  CTSC is asserted, the UARTx_CTS output pin is
//  controlled by the receiver. When the RxFIFO is
//  filled to the level of the programmed trigger
//  level and the start bit of the overflowing
//  character (TRIGGER LEVEL + 1) is validated, the
//  UARTx_CTS output pin is negated to indicate to
//  the far-end transmitter to stop transmitting.
//  When the trigger level is programmed for less
//  than 32, the receiver continues to receive data
//  until the RxFIFO is full. When the CTSC bit is
//  negated, the UARTx_CTS output pin is controlled
//  by the CTS bit. On reset, because CTSC is
//  cleared to 0, the UARTx_CTS pin is controlled
//  by the CTS bit, which again is cleared to 0 on
//  reset. This means that on reset the UARTx_CTS
//  signal is negated.
//-------------------------------------------------*/
 void
uart2_CTS_Automatic(uint32_t);//

/*---------------------------------------------------
// CTS, UCR2[12] = 0
//   Result: The  UARTx_CTS pin is high (inactive)
//
//  Clear to Send --Controls the UARTx_CTS pin
//  when the CTSC bit is negated. CTS has no
//  function when CTSC is asserted.
//-------------------------------------------------*/
 void
uart2_CTS_Deassert(void);//


/*---------------------------------------------------
// CTS, UCR2[12] = 1
//   Result: The UARTx_CTS pin is low (active)
//
//  Clear to Send --Controls the UARTx_CTS pin
//  when the CTSC bit is negated. CTS has no
//  function when CTSC is asserted.
//-------------------------------------------------*/
 void
uart2_CTS_Assert(void);//


/*---------------------------------------------------
// ESCEN, UCR2[11] = Enable/Disable
//
//  Escape Enable --Enables/Disables the escape
//  sequence detection logic.
//-------------------------------------------------*/
 void
uart2_RxEscapeDetect(uint32_t);//


/*---------------------------------------------------
// FIX ME
// RTEC, UCR2[10-9] = ??
//   Result: Trigger interrupt on a rising edge
//
//  Request to Send Edge Control --Selects the
//  edge that triggers the RTS interrupt. This has
//  no effect on the RTS delta interrupt. RTEC has
//  an effect only when RTSEN = 1 (see ).
//-------------------------------------------------*/
 void
uart2_RTS_EdgeControl(uint32_t);//


/*---------------------------------------------------
// PREN, UCR2[8] = Enable/Disable
//
//  Parity Enable --Enables/Disables the parity
//  generator in the transmitter and parity checker
//  in the receiver. When PREN is asserted, the
//  parity generator and checker are enabled, and
//  disabled when PREN is negated.
//-------------------------------------------------*/
 void
uart2_Parity(uint32_t);//


/*---------------------------------------------------
// PROE, UCR2[7] = _EvenParity/_OddParity (0/1)
//   Result: Even or Odd parity
//
//  Parity Odd/Even --Controls the sense of the
//  parity generator and checker. When PROE is
//  high, odd parity is generated and expected.
//  When PROE is low, even parity is generated and
//  expected. PROE has no function if PREN is low.
//-------------------------------------------------*/
 void
uart2_ParityType(uint32_t);//


/*---------------------------------------------------
// STPB, UCR2[6] = Enable/Disable
//   Result: 2 stop bits if enabled, else 1
//
//  Stop --Controls the number of stop bits
//  transmitted after a character. When STPB is
//  high, 2 stop bits are sent. When STPB is low, 1
//  stop bit is sent. STPB has no effect on the
//  receiver, which expects 1 or more stop bits.
//-------------------------------------------------*/
 void
uart2_ExtraStopBit(uint32_t);//


/*---------------------------------------------------
// WS, UCR2[5] = _8bitUART/_7bitUART (1/0)
//   Result: '0' or '_7bitUART' results in 7-bit,
//    '1' or '_8bitUART' results in 8-bit transmit
//    and receive character length (not including
//    START, STOP or PARITY bits)
//
//  Word Size --Controls the character length.
//  When WS is high, the transmitter and receiver
//  are in 8-bit mode. When WS is low, they are in
//  7-bit mode. The transmitter ignores bit 7 and
//  the receiver sets bit 7 to 0. WS can be changed
//  in-between transmission (reception) of
//  characters, however not when a transmission
//  (reception) is in progress, in which case the
//  length of the current character being
//  transmitted (received) is unpredictable.
//  At restart defaults to 7-bit.
//-------------------------------------------------*/
 void
uart2_CharacterWidth(uint32_t);//


/*---------------------------------------------------
// RTSEN, UCR2[4] = Enable/Disable
//
//  Request to Send Interrupt Enable --Controls
//  the RTS edge sensitive interrupt. When RTSEN is
//  asserted and the programmed edge is detected on
//  the UARTx_RTS pin, the RTSF bit is asserted
//  (see ).
//-------------------------------------------------*/
 void
uart2_RTS_EdgeInterrupt(uint32_t);//


/*---------------------------------------------------
// ATEN, UCR2[3] = Enable/Disable
//
//  Aging Timer Enable --This bit is used to
//  mask the aging timer interrupt (triggered with
//  AGTIM).
//-------------------------------------------------*/
 void
uart2_AgingCharacterDetectInterrupt(uint32_t);


/*---------------------------------------------------
// TXEN, UCR2[2] = Enable/Disable
//
//  Transmitter Enable --Enables/Disables the
//  transmitter. When TXEN is negated the
//  transmitter is disabled and idle. When the
//  UARTEN and TXEN bits are set the transmitter is
//  enabled. If TXEN is negated in the middle of a
//  transmission, the UART disables the transmitter
//  immediately.
//-------------------------------------------------*/
 void
uart2_Tx(uint32_t);//


/*---------------------------------------------------
// RXEN, UCR2[1] = Enable/Disable
//
//  Receiver Enable --Enables/Disables the
//  receiver. When the receiver is enabled, if the
//  RXD input is already low, the receiver does not
//  recognize BREAK characters, because it requires
//  a valid 1-to-0 transition before it can accept
//  any character.
//-------------------------------------------------*/
 void
uart2_Rx(uint32_t);//


/*---------------------------------------------------
// SRST, UCR2[0] = 0
//   Result: Reset the transmit and receive state
//    machines, all FIFOs and all status registers
//
//  Software Reset --Resets the transmitter and
//  receiver state machines, all FIFOs, and all
//  status registers. Once the software writes 0 to
//   SRST , the software reset remains active for 4
//  clock cycles of ipg_clk before the hardware
//  deasserts  SRST . The software can only write 0
//  to	SRST . Writing 1 to  SRST is ignored.
//-------------------------------------------------*/
 void
uart2_SoftReset(void);//


/*---------------------------------------------------
// PARERREN, UCR3[12] = Enable/Disable
//
//  Parity Error Interrupt Enable
//  --Enables/Disables the interrupt. When
//  asserted, PARERREN causes the PARITYERR bit to
//  generate an interrupt.
//-------------------------------------------------*/
 void
uart2_RxParityErrorInterrupt(uint32_t);//


/*---------------------------------------------------
// FRAERREN, UCR3[11] = Enable/Disable
//
//  Frame Error Interrupt Enable
//  --Enables/Disables the interrupt. When
//  asserted, FRAERREN causes the FRAMERR bit to
//  generate an interrupt.
//-------------------------------------------------*/
 void
uart2_RxFrameErrorInterrupt(uint32_t);//


/*---------------------------------------------------
// RXDSEN, UCR3[6] = Enable/Disable
//
// Receive Status Interrupt Enable--Controls
//  the receive status interrupt. When this bit is
//  enabled and RXDS status bit is set, the
//  interrupt will be generated.
//-------------------------------------------------*/
 void
uart2_RxIdleStatusInterrupt(uint32_t);//


/*---------------------------------------------------
// AIRINTEN, UCR3[5] = Enable/Disable
//
// Asynchronous IR WAKE Interrupt
//  Enable--Controls the asynchronous IR WAKE
//  interrupt. An interrupt is generated when
//  AIRINTEN is asserted and a pulse is detected on
//  the UART_RX pin.
//-------------------------------------------------*/
 void
uart2_IR_AsyncWakeInterrupt(uint32_t);


/*---------------------------------------------------
// AWAKEN, UCR3[4] = Enable/Disable
//
// Asynchronous WAKE Interrupt Enable--Controls
//  the asynchronous WAKE interrupt. An interrupt
//  is generated when AWAKEN is asserted and a
//  falling edge is detected on the RXD pin.
//-------------------------------------------------*/
 void
uart2_AsyncWakeInterrupt(uint32_t);

/*---------------------------------------------------