mx21_crm.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/*---------------------------------------------------
// SSI1DIV, PCDR0[21:16] = 0..63
// functions like SSI2DIV
//-------------------------------------------------*/
 void
pllclk_SSI1_Divider(uint32_t);

/*---------------------------------------------------
// Pass desired divider to function, it will match
// as closely as possible and return the divider
// value which was set.
//-------------------------------------------------*/
// NOT YET IMPLEMENTED
uint32_t
pllclk_SSI2_AutoDivider(uint32_t);
uint32_t
pllclk_SSI1_AutoDivider(uint32_t);

/*---------------------------------------------------
// NFCDIV, PCDR0[15:12] = 0..15
// NFCCLK
// Nand Flash Controller Clk Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_NFC_Divider(uint32_t);

/*---------------------------------------------------
// CLKO_48MDIV, PCDR0[7:5] = 0..8
// CLK48DIV_CLKO
// Clock Out 48M Divider 1 = n + 1
//-------------------------------------------------*/
 void
pllclk_CLKO48M_Divider(uint32_t);

/*---------------------------------------------------
// FIRI_DIV, PCDR0[4:0] = 0..31
// FIRICLK
// FIRI Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_FIRI_Divider(uint32_t);

/***PCDR1***/

/*---------------------------------------------------
// PERDIV4, PCDR1[29:24] = 0..63
// PERCLK4 : CSI MCLK
// Peripheral Clock 4 Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_PERCLK4_Divider(uint32_t);

/*---------------------------------------------------
// PERDIV3, PCDR1[21:16] = 0..63
// PERCLK3 : LCDC
// Peripheral Clock 3 Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_PERCLK3_Divider(uint32_t);

/*---------------------------------------------------
// PERDIV2, PCDR1[13:8] = 0..63
// PERCLK2 : CSPI, SDHC
// Peripheral Clock 2 Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_PERCLK2_Divider(uint32_t);

/*---------------------------------------------------
// PERDIV1, PCDR1[5:0] = 0..63
// PERCLK1 : UART, GPT, PWM
// Peripheral Clock 1 Divider = n + 1
//-------------------------------------------------*/
 void
pllclk_PERCLK1_Divider(uint32_t);

/***PCCR0***/

/*---------------------------------------------------
// HCLK_CSI, PCCR0[31] = Enable/Disable 
// Enable/Disable HCLK clock input to the CSI module
//-------------------------------------------------*/
 void
pllclk_CSI_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_DMA, PCCR0[30] = Enable/Disable 
// Enable/Disable HCLK clock input to the DMA module
//-------------------------------------------------*/
 void
pllclk_DMA_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_BROM, PCCR0[28] = Enable/Disable 
// Enable/Disable HCLK clock input to the BROM module
//-------------------------------------------------*/
 void
pllclk_BROM_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_EMMA, PCCR0[27] = Enable/Disable 
// Enable/Disable HCLK clock input to the EMMA module
//-------------------------------------------------*/
 void
pllclk_EMMA_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_LCDC, PCCR0[26] = Enable/Disable 
// Enable/Disable HCLK clock input to the LCDC module
//-------------------------------------------------*/
 void
pllclk_LCDC_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_SLDCD, PCCR0[25] = Enable/Disable 
// Enable/Disable HCLK clock input to the SLCDC module
//-------------------------------------------------*/
 void
pllclk_SLCDC_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_USBOTG, PCCR0[24] = Enable/Disable 
// Enable/Disable HCLK clock input to the USB OTG module
//-------------------------------------------------*/
 void
pllclk_USB_HCLK(uint32_t);

/*---------------------------------------------------
// HCLK_BMI, PCCR0[23] = Enable/Disable 
// Enable/Disable HCLK clock input to the BMI module
//-------------------------------------------------*/
 void
pllclk_BMI_HCLK(uint32_t);

/*---------------------------------------------------
// PERCLK4, PCCR0[22] = Enable/Disable 
// Enable/Disable peripheral clock input to CSI module
//-------------------------------------------------*/
 void
pllclk_CSI_Clk(uint32_t);

/*---------------------------------------------------
// SLDCD, PCCR0[21] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the SLCDC module
//-------------------------------------------------*/
 void
pllclk_SLCDC_Clk(uint32_t);

/*---------------------------------------------------
// FIRI_BAUD, PCCR0[20] = Enable/Disable 
// Enable/Disable baud rate clock input to the FIRI module
//-------------------------------------------------*/
 void
pllclk_FIRI_BAUD_Clk(uint32_t);

/*---------------------------------------------------
// NFC, PCCR0[19] = Enable/Disable 
// Enable/Disable clock input to the NFC module
//-------------------------------------------------*/
 void
pllclk_NFC_Clk(uint32_t);

/*---------------------------------------------------
// PERCLK3, PCCR0[18] = Enable/Disable 
// Enable/Disable pixel clock input to the LCDC module
//-------------------------------------------------*/
 void
pllclk_LCDC_Clk(uint32_t);

/*---------------------------------------------------
// SSI1_BAUD, PCCR0[17] = Enable/Disable 
// Enable/Disable baud rate clock input to the SSI1 module
//-------------------------------------------------*/
 void
pllclk_SSI1_BAUD_Clk(uint32_t);

/*---------------------------------------------------
// SSI2_BAUD, PCCR0[16] = Enable/Disable 
// Enable/Disable baud rate clock input to the SSI2 module
//-------------------------------------------------*/
 void
pllclk_SSI2_BAUD_Clk(uint32_t);

/*---------------------------------------------------
// EMMA, PCCR0[15] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the EMMA module
//-------------------------------------------------*/
 void
pllclk_EMMA_Clk(uint32_t);

/*---------------------------------------------------
// USBOTG, PCCR0[14] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the USB OTG module
//-------------------------------------------------*/
 void
pllclk_USB_Clk(uint32_t);

/*---------------------------------------------------
// DMA, PCCR0[13] = Enable/Disable 
// Enable/Disable ipg clock input to the DMA module
//-------------------------------------------------*/
 void
pllclk_DMA_Clk(uint32_t);

/*---------------------------------------------------
// I2C, PCCR0[12] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the I2C module
//-------------------------------------------------*/
 void
pllclk_I2C_Clk(uint32_t);

/*---------------------------------------------------
// GPIO, PCCR0[11] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the GPIO module
//-------------------------------------------------*/
 void
pllclk_GPIO_Clk(uint32_t);

/*---------------------------------------------------
// SDHC2, PCCR0[10] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the SDHC2 module
//-------------------------------------------------*/
 void
pllclk_SDHC2_Clk(uint32_t);

/*---------------------------------------------------
// SDHC1, PCCR0[9] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the SDHC1 module
//-------------------------------------------------*/
 void
pllclk_SDHC1_Clk(uint32_t);

/*---------------------------------------------------
// FIRI, PCCR0[8] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the FIRI module
//-------------------------------------------------*/
 void
pllclk_FIRI_Clk(uint32_t);

/*---------------------------------------------------
// SSI2, PCCR0[7] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the SSI2 module
//-------------------------------------------------*/
 void
pllclk_SSI2_Clk(uint32_t);

/*---------------------------------------------------
// SSI1, PCCR0[6] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the SSI1 module
//-------------------------------------------------*/
 void
pllclk_SSI1_Clk(uint32_t);

/*---------------------------------------------------
// CSPI2, PCCR0[5] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the CSPI2 module
//-------------------------------------------------*/
 void
pllclk_CSPI2_Clk(uint32_t);

/*---------------------------------------------------
// CSPI1, PCCR0[4] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the CSPI1 module
//-------------------------------------------------*/
 void
pllclk_CSPI1_Clk(uint32_t);

/*---------------------------------------------------
// UART4, PCCR0[3] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the UART4 module
//-------------------------------------------------*/
 void
pllclk_UART4_Clk(uint32_t);

/*---------------------------------------------------
// UART3, PCCR0[2] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the UART3 module
//-------------------------------------------------*/
 void
pllclk_UART3_Clk(uint32_t);

/*---------------------------------------------------
// UART2, PCCR0[1] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the UART2 module
//-------------------------------------------------*/
 void
pllclk_UART2_Clk(uint32_t);

/*---------------------------------------------------
// UART1, PCCR0[0] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the UART1 module
//-------------------------------------------------*/
 void
pllclk_UART1_Clk(uint32_t);



/***PCCR1***/



/*---------------------------------------------------
// OWIRE, PCCR1[31] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the OWIRE module
//-------------------------------------------------*/
 void
pllclk_OWIRE_Clk(uint32_t);

/*---------------------------------------------------
// KPP, PCCR1[30] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the KPP module
//-------------------------------------------------*/
 void
pllclk_KPP_Clk(uint32_t);

/*---------------------------------------------------
// RTC, PCCR1[29] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the RTC module
//-------------------------------------------------*/
 void
pllclk_RTC_Clk(uint32_t);

/*---------------------------------------------------
// PWM, PCCR1[28] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the PWM module
//-------------------------------------------------*/
 void
pllclk_PWM_Clk(uint32_t);

/*---------------------------------------------------
// GPT3, PCCR1[27] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the GPT3 module
//-------------------------------------------------*/
 void
pllclk_GPT3_Clk(uint32_t);

/*---------------------------------------------------
// GPT2, PCCR1[26] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the GPT2 module
//-------------------------------------------------*/
 void
pllclk_GPT2_Clk(uint32_t);

/*---------------------------------------------------
// GPT1, PCCR1[25] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the GPT1 module
//-------------------------------------------------*/
 void
pllclk_GPT1_Clk(uint32_t);

/*---------------------------------------------------
// WDT, PCCR1[24] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the WDT module
//-------------------------------------------------*/
 void
pllclk_WDT_Clk(uint32_t);

/*---------------------------------------------------
// CSPI3, PCCR1[23] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the CSPI3 module
//-------------------------------------------------*/
 void
pllclk_CSPI3_Clk(uint32_t);

/*---------------------------------------------------
// RTIC, PCCR1[22] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the RTIC module
//-------------------------------------------------*/
 void
pllclk_RTIC_Clk(uint32_t);

/*---------------------------------------------------
// RNGA, PCCR1[21] = Enable/Disable 
// Enable/Disable peripheral clock ipg clock (PERCLK) input to
//  the RNGA module
//-------------------------------------------------*/
 void
pllclk_RNGA_Clk(uint32_t);



/***CCSR***/

/*---------------------------------------------------
// 32K_SR, CCSR[15]
// Reads the status of the 32KHz clock.
// Returns '1' if high, '0' if low
//-------------------------------------------------*/
 uint32_t
pllclk_32K_ClkStatus(void);

/*---------------------------------------------------
// CKLO_SEL, CCSR[4:0] = 0..21
// Select the clock signal to be output on the CLKO pin
//
// 00000 =00= CLK32
// 00001 =01= PREMCLK
// 00010 =02= CLK26M
// 00011 =03= MPLL Reference CLK
// 00100 =04= SPLL Reference CLK
// 00101 =05= MPLL CLK
// 00110 =06= SPLL CLK
// 00111 =07= FCLK
// 01000 =08= HCLK
// 01001 =09= IPG_CLK (PERCLK)
// 01010 =10= PERCLK1
// 01011 =11= PERCLK2
// 01100 =12= PERCLK3
// 01101 =13= PERCLK4
// 01110 =14= SSI 1 Baud
// 01111 =15= SSI 2 Baud
// 10000 =16= NFC Baud
// 10001 =17= FIRI Baud
// 10010 =18= CLK48M Always
// 10011 =19= CLK32K Always
// 10100 =20= CLK48M
// 10101 =21= CLK48DIV_CLKO
//--------------------------------------------------*/
 void
pllclk_CLKO_Select(uint32_t);

/***WKGDCTL***/

/*----------------------------------------------------
// WKDG_EN, WKGDCTL[0] = 1
// Enable wakeup guard mode logic. Can only be disabled
//  through a system rest.
//--------------------------------------------------*/
 void
pllclk_WakeupGuardModeEnable(void);

#endif /* _MX21CRM_H_ */