mx21_crm.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division:  WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name:        MX21_CRM.h
*     Revision Number:  0.1
*     Author(s):        Ryan Johnson
*     Date created:     22 June 2004
*     Revision History:
*        Date      Rev     Description
*        ----      ---     -----------
*        22June04  0.1     First draft
*        12July04  0.2     Clk Freq functions & tweaking
*
**********************************************************************/

#ifndef _MX21CRM_H_
#define _MX21CRM_H_

#include "MX21_MemMap.h"
#include "MX21_Macros.h"
#include "MX21_DataTypes.h"
#include "MX21_Common.h"

/********************************************************************
M A C R O S
*********************************************************************/

#define _32K                           16777216
#define _26M                           26000000

/********************************************************************
F U N C T I O N   P R O T O T Y P E S
*********************************************************************/

/*** Frequency Set/Read Functinos ***/

/*---------------------------------------------------
// Used to set MPLL clock frequency.
// The parameter is the desired frequency setting
//  of the MPLL.
// The actual frequency is returned.
//-------------------------------------------------*/
uint32_t
pllclk_MPLL_SetFrequency(uint32_t);

/*---------------------------------------------------
// See description above
//-------------------------------------------------*/
uint32_t
pllclk_SPLL_SetFrequency(uint32_t);


/*---------------------------------------------------
// These functions return the frequency of their clock
//-------------------------------------------------*/
uint32_t
pllclk_MPLL_Frequency(void);
uint32_t
pllclk_SPLL_Frequency(void);
 uint32_t
pllclk_FCLK_Frequency(void);
 uint32_t
pllclk_HCLK_Frequency(void);
 uint32_t
pllclk_PERCLK_Frequency(void);
 uint32_t
pllclk_PERCLK1_Frequency(void);
 uint32_t
pllclk_PERCLK2_Frequency(void);
 uint32_t
pllclk_PERCLK3_Frequency(void);
 uint32_t
pllclk_PERCLK4_Frequency(void);
uint32_t
pllclk_FIRICLK_Frequency(void);
 uint32_t
pllclk_CLK48M_Frequency(void);
uint32_t
pllclk_SSI1CLK_Frequency(void);
uint32_t
pllclk_SSI2CLK_Frequency(void);


/***CSCR***/

/*---------------------------------------------------
//  PRESC, CSCR[31:29] = 0..7
//  Defines the MPU PLL clock 3-bit prescaler as n+1
//-------------------------------------------------*/
 void 
pllclk_SetPrescaler(uint32_t);  

/*---------------------------------------------------
// USB_DIV, CSCR[28:26] = 0..7
// Sets the 3-bit divider for generation of CLK48M as n+1
//-------------------------------------------------*/
 void
pllclk_USB_Divider(uint32_t);

/*---------------------------------------------------
// SD_CNT, CSCR[25:24] = 0..3
// when 0 is written to the MPEN of SPEN bit,
// DPLL shutdown after the (n+1)th rising edge of CLK32
// is detected and the current bus cycle is completed
//-------------------------------------------------*/
 void
pllclk_ShutdownControl(uint32_t);

/*---------------------------------------------------
// SPLL_RESTART, CSCR[22] = 1
// Restarts SPLL at new frequency
//-------------------------------------------------*/
 void
pllclk_SPLL_Restart(void);

/*---------------------------------------------------
// MPLL_RESTART, CSCR[21] = 1
// Restarts MPLL at new frequency
//-------------------------------------------------*/
 void
pllclk_MPLL_Restart(void);

/*---------------------------------------------------
// SSI2_SEL, CSCR[20] = 0
// SSI2 clk from SPLL
//-------------------------------------------------*/
 void
pllclk_SSI2_SPLL(void);

/*---------------------------------------------------
// SSI2_SEL, CSCR[20] = 1
// SSI2 clk from MPLL
//-------------------------------------------------*/
 void
pllclk_SSI2_MPLL(void);

/*---------------------------------------------------
// SSI1_SEL, CSCR[19] = 0
// SSI1 clk from SPLL
//-------------------------------------------------*/
 void
pllclk_SSI1_SPLL(void);

/*---------------------------------------------------
// SSI1_SEL, CSCR[19] = 1
// SSI1 clk from MPLL
//-------------------------------------------------*/
 void
pllclk_SSI1_MPLL(void);

/*---------------------------------------------------
// FIR_SEL, CSCR[18] = 1
// FIRI clk from SPLL
//-------------------------------------------------*/
 void
pllclk_FIRI_SPLL(void);

/*---------------------------------------------------
// FIR_SEL, CSCR[18] = 0
// FIRI clk from MPLL
//-------------------------------------------------*/
 void
pllclk_FIRI_MPLL(void);

/*---------------------------------------------------
// SP_SEL, CSCR[17] = 1
// SPLL clk from external 26MHz crystal/source
//-------------------------------------------------*/
 void
pllclk_SPLL_26M(void);

/*---------------------------------------------------
// SP_SEL, CSCR[17] = 0
// SPLL clock from premultiplier fed by 32KHz crystal
//-------------------------------------------------*/
 void
pllclk_SPLL_32K(void);

/*---------------------------------------------------
// MCU_SEL, CSCR[16] = 1
// MPLL clock from external 26MHz crystal/source
//-------------------------------------------------*/
 void
pllclk_MPLL_26M(void);

/*---------------------------------------------------
// MCU_SEL, CSCR[16] = 0
// MPLL clcok from premultiplier fed by 32KHz crystal
//-------------------------------------------------*/
 void
pllclk_MPLL_32K(void);

/*---------------------------------------------------
// BCLKDIV, CSCR[13:10] = 0..15
// 4-bit divider for HCLK = BCLK/(n+1)
//-------------------------------------------------*/
 void
pllclk_BCLK_Divider(uint32_t);

/*---------------------------------------------------
// IPDIV, CSCR[9] = 0..1
// Peripheral Clock Divider, PERCLK = HCLK/(n+1)
//-------------------------------------------------*/
 void
pllclk_PERCLK_Divider(uint32_t);

/*---------------------------------------------------
// OSC26M_DIV1P5, CSCR[4] = 0..1
// 26MHz oscillator divider, full speed if '0', divide
// by 1.5 if '1'
//-------------------------------------------------*/
 void
pllclk_OSC26M_Divider(uint32_t);

/*---------------------------------------------------
// OSC26M_EN, CSCR[3] = Enable/Disable
// Enable or Disable the external 26 MHz oscillator
//  circuit
//-------------------------------------------------*/
 void
pllclk_OSC26M(uint32_t);

/*---------------------------------------------------
// FPM_EN, CSCR[2] = Enable/Disable
// Enable or Disable the frequency premultiplier
// circuit
//-------------------------------------------------*/
 void
pllclk_FPM(uint32_t);

/*---------------------------------------------------
// SPEN, CSCR[1] = Enable/Disable
// Enables the SPLL
//-------------------------------------------------*/
 void
pllclk_SPLL(uint32_t);

/*---------------------------------------------------
// MPEN, CSCR[0] = Enable/Disable
// Enables the MPLL
//-------------------------------------------------*/
 void
pllclk_MPLL(uint32_t);


/***MPCTL0***/

// MPLL frequency = 2 * Reference_Freq * (MFI + MFN/(MFD+1))/(PD+1)

/*---------------------------------------------------
// CPLM, MPCTL0[31] = 0
// DPLL operates in the Frequency Only Lock mode
//-------------------------------------------------*/
 void
pllclk_MPLL_FrequencyOnlyLock(void);

/*---------------------------------------------------
// CPLM, MPCTL0[31] = 1
// DPLL operates in Frequency & Phase Lock mode.
//-------------------------------------------------*/
 void
pllclk_MPLL_FrequencyPhaseLock(void);

/*---------------------------------------------------
// PD, MPCTL0[29:26] = 0..15
// Predivider Factor for MPLL
//-------------------------------------------------*/
 void
pllclk_MPLL_Predivider(uint32_t);

/*---------------------------------------------------
// MFD, MPCTL0[25:16] = 1..1023
// Denominator of the MPLL multiplier fractional
// portion.
//-------------------------------------------------*/
 void
pllclk_MPLL_Multiplier_Denominator(uint32_t);

/*---------------------------------------------------
// MFI, MPCTL0[13:10] = 0..15
// Integer part of the MPLL multiplier
//-------------------------------------------------*/
 void
pllclk_MPLL_Multiplier_Integer(uint32_t);

/*---------------------------------------------------
// MFN, MPCTL0[9:0] = 0..1022
// Numerator of the MPLL multiplier fractional
// portion.
//-------------------------------------------------*/
 void
pllclk_MPLL_Multiplier_Numerator(uint32_t);

/***MPCTL1***/

/*---------------------------------------------------
// LF, MPCTL1[15] = 1
// Lock the MPLL, making its output valid
//-------------------------------------------------*/
 void
pllclk_MPLL_Lock(void);

/*---------------------------------------------------
// LF, MPCTL1[15] = 0
// Unlock the MPLL, causing the output to remain
// at logic high
//-------------------------------------------------*/
 void
pllclk_MPLL_Unlock(void);

/*---------------------------------------------------
// BRMO, MPCTL1[6] = 0
// Configures BRM to first order, used if the MF
// fractional part is greater than 1/10 & less than 9/10
//-------------------------------------------------*/
 void
pllclk_MPLL_BRM_FirstOrder(void);

/*---------------------------------------------------
// BRMO, MPCTL1[6] = 1
// Configures BRM to second order, used if the MF
// fractional part is less than 1/10 or more than 9/10
//-------------------------------------------------*/
 void
pllclk_MPLL_BRM_SecondOrder(void);

/***SPCTL0***/

// Pll frequency = 2 * Reference_Freq * (MFI + MFN/(MFD+1))/(PD+1)

/*---------------------------------------------------
// CPLM, SPCTL0[31] = 0
// DPLL operates in the Frequency Only Lock mode
//-------------------------------------------------*/
 void
pllclk_SPLL_FrequencyOnlyLock(void);

/*---------------------------------------------------
// CPLM, SPCTL0[31] = 1
// DPLL operates in Frequency & Phase Lock mode.
//-------------------------------------------------*/
 void
pllclk_SPLL_FrequencyPhaseLock(void);

/*---------------------------------------------------
// PD, SPCTL0[29:26] = 0..15
// Predivider Factor for SPLL
//-------------------------------------------------*/
 void
pllclk_SPLL_Predivider(uint32_t);

/*---------------------------------------------------
// MFD, SPCTL0[25:16] = 1..1023
// Denominator of the SPLL multiplier fractional
// portion.
//-------------------------------------------------*/
 void
pllclk_SPLL_Multiplier_Denominator(uint32_t);

/*---------------------------------------------------
// MFI, SPCTL0[13:10] = 0..15
// Integer part of the SPLL multiplier
//-------------------------------------------------*/
 void
pllclk_SPLL_Multiplier_Integer(uint32_t);

/*---------------------------------------------------
// MFD, SPCTL0[9:0] = 0..1022
// Numerator of the SPLL multiplier fractional
// portion.
//-------------------------------------------------*/
 void
pllclk_SPLL_Multiplier_Numerator(uint32_t);

/***SPCTL1***/

/*---------------------------------------------------
// LF, SPCTL1[15] = 1
// Lock the SPLL, making its output valid
//-------------------------------------------------*/
 void
pllclk_SPLL_Lock(void);

/*---------------------------------------------------
// LF, SPCTL1[15] = 0
// Unlock the SPLL, causing the output to remain
// at logic high
//-------------------------------------------------*/
 void
pllclk_SPLL_Unlock(void);

/*---------------------------------------------------
// BRMO, SPCTL1[6] = 0
// Configures BRM to first order, used if the MF
// fractional part is greater than 1/10 & less than 9/10
//-------------------------------------------------*/
 void
pllclk_SPLL_BRM_FirstOrder(void);

/*---------------------------------------------------
// BRMO, SPCTL1[6] = 1
// Configures BRM to second order, used if the MF
// fractional part is less than 1/10 or more than 9/10
//-------------------------------------------------*/
 void
pllclk_SPLL_BRM_SecondOrder(void);

/***OSC26MCTL***/

/*---------------------------------------------------
// AGC, OSC26MCTL[13:8] = 0..63
// Write a previously  calculated trim value for
// the Automatic Gain Control of the 26MHz oscillator
//-------------------------------------------------*/
 void
pllclk_OSC26M_AutomaticGainControl(uint32_t AGC);

/*---------------------------------------------------
// OSC26M_PEAK, OSC26MCTL[17:16]
// Used to check amplitude of 26 MHz oscillator
// returns 0 = desired operating range,
//         1 = amplitude too low
//         2 = amplitude too high
//         3 = invalid state
//-------------------------------------------------*/
 uint32_t
pllclk_OSC26M_AmplitudeCheck(void);

/*---------------------------------------------------
// Sets the 26MHz oscillator trim automatically, and
// returns the determined value of the AGC.
// Note that this function may take several hundred
// thousand clock cycles to complete (still << 1 sec).
// Returns 0xFFFFFFFF if the tuning fails.
//-------------------------------------------------*/
uint32_t
pllclk_OSC26M_AutoTrim(void);


/***PCDR0***/

/*---------------------------------------------------
// SSI2DIV, PCDR0[31:26] = 0..63
// SSI2 Bauc Clock Divider = 62 for n=0 or 1
// for others = clkin/(SSI2DIV[high:1] + .5*SSI2DIV[0])
// e.g. 13 = 001101 = clkin/(0b00110 + .5*1)=clkin/6.5
//-------------------------------------------------*/
 void
pllclk_SSI2_Divider(uint32_t);