mx21_armcore.h

MX21_InitCodeLib.rar freescale mx21系列ARM芯片9328的WINCE5.0下初始化代码

/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division:  WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name:        MX21_ArmCore.h
*     Revision Number:  0.1
*     Author(s):        Sharad Kumar
*     Date created:     30Apr2004
*     Revision History:
*        Date      Rev     Description
*        ----      ---     -----------
*        30Apr04  0.1     First draft
*
**********************************************************************/

#ifndef _MX21_ARMCORE_H
#define _MX21_ARMCORE_H


#include "MX21_DataTypes.h"
#include "MX21_Macros.h"
#include "MX21_Common.h"
#include "MX21_PageTable.h"

//********************************************************************
// M A C R O S
//********************************************************************

#define CPU_IRQ_DIS_BIT		      0x80     // CPSR IRQ Bit
#define	CPU_FIQ_DIS_BIT	          0x40     // CPSR FIQ Bit
#define CPU_MODE_MASK			  0x1F     // CPSR, Mode  Mask
#define CPU_MODE_USR			  0x10     // CPSR, User  mode
#define CPU_MODE_FIQ			  0x11     // CPSR, FIQ   mode
#define CPU_MODE_IRQ			  0x12     // CPSR, IRQ   mode
#define CPU_MODE_SUP			  0x13     // CPSR, Sup   mode
#define CPU_MODE_ABT			  0x17     // CPSR, Abort mode
#define CPU_MODE_UND			  0x1B     // CPSR, Undef mode
#define CPU_MODE_SYS			  0x1F     // CPSR, Sys   mode


#define ENABLE_I_CACHE            0x1000   	   // CP15, control reg, I bit 
#define ENABLE_D_CACHE            0x4          // CP15, control reg, C bit 
#define ENABLE_WRT_BUF            0x8          // CP15, control reg, W bit    			  
#define ENABLE_MMU                0x1          // CP15, control reg, M bit 


#define DOMAIN_ACCESS             0xFFFFFFFF   // all 16 domains have manager
                                               // access types.  
#define CPU_IDCODES_CACHETYPE     0x1          // "cache type" return val from 
                                               // ID codes register
//---------------------------------------------------
// enumeration for cache types supported
// by the ARM926EJ-S core
//---------------------------------------------------
typedef enum { 
			    CACHE_INST       = 0,  // Instruction
			    CACHE_DATA       = 1,  // Data
			    CACHE_INST_DATA  = 2,  // Instruction & Data
			    CACHE_LEVEL2     = 3   // Level 2 cache
			  } cache_type;



//********************************************************************
// F U N C T I O N   P R O T O T Y P E S
//********************************************************************



//---------------------------------------------------
// Read the device ID or cache type.
// default selection is device ID. 
// use ARM_IDCODES_CACHETYPE as the
// parameter if cache type is to
// be read.
//---------------------------------------------------
uint32_t                               // device id, or cache type
ARM_DeviceIDRead(uint32_t);			   // select between device id or cache type


//---------------------------------------------------
// Initialize the MMU. This routine uses the following
// functions to setup the MMU:
//    ARM_TLBFlush(...)
//    ARM_CacheFlush(...)
//    ARM_SetDomainAccessControl(...)
//    ARM_SetPageTableBase(...)
// The MMU table base address must be passed as an 
// argument. 
// The MMU table base address is a return parameter of 
// the routine ARM_MMUTableSetUp()), defined in the file
// MX21_PageTable.h
//
// Typical use of this function in user programs is:
// ARM_MMU_Init((p_uint32_t) ARM_MMUTableSetUp());
//---------------------------------------------------
void 
ARM_MMUInit(p_uint32_t);  // page table base address



//---------------------------------------------------
// enable the MMU. Use this function to enable MMU
// once the MMU has been initialized.
//---------------------------------------------------
void 
ARM_MMUEnable(void);

 
//---------------------------------------------------
// disable the MMU
//---------------------------------------------------
void 
ARM_MMUDisable(void);


//---------------------------------------------------
// set the base address for the page tables. 
// is also called by ARM_MMUInit(...) function
//---------------------------------------------------
void 
ARM_SetPageTableBase(p_uint32_t);      // table address


//---------------------------------------------------
// Set domain access control bits, CP15, register 3
// is also called by ARM_MMUInit(...) function
//---------------------------------------------------
void 
ARM_SetDomainAccessControl(uint32_t);  // 32 bit vector


//---------------------------------------------------
// Flush the TLB, required before enabling
// the MMU
// is also called by ARM_MMUInit(...) function
//---------------------------------------------------
void 
ARM_TLBFlush(void);


//---------------------------------------------------
// flush the instruction cache, required before
// enabling the MMU
//---------------------------------------------------
void 
ARM_ICacheFlush();

//---------------------------------------------------
// flush the data cache, required before
// enabling the MMU
//---------------------------------------------------
void 
ARM_DCacheFlush();

//---------------------------------------------------
// flush the instruction and data cache, required before
// enabling the MMU
//---------------------------------------------------
void 
ARM_CacheFlush();


//---------------------------------------------------------------
// This function is used to enable Instruction, and/or Data Cache
// Cache Type is:
//   { CACHE_INST, CACHE_DATA, CACHE_INST_DATA, CACHE_LEVEL2 }
// Level 2 cache is not available or supported on MX21
// Note: the MMU must be enabled 
// for D cache to work properly.
//---------------------------------------------------------------
void 
ARM_EnableCache(cache_type);

//---------------------------------------------------------------
// This function is used to disable Instruction, and/or Data Cache
// Cache Type is:
//   { CACHE_INST, CACHE_DATA, CACHE_INST_DATA, CACHE_LEVEL2 }
// Level 2 cache is not available or supported on MX21
//---------------------------------------------------------------
void 
ARM_DisableCache(cache_type);


//---------------------------------------------------
// enable the instruction cache
//---------------------------------------------------
void 
ARM_ICacheEnable(void);


//---------------------------------------------------
// enable the data cache
// Note: the MMU must be enabled 
// for D cache to work properly.
//---------------------------------------------------
void 
ARM_DCacheEnable(void);


//---------------------------------------------------
// enable the instruction & data cache's
//---------------------------------------------------
void 
ARM_IDCacheEnable(void);


//---------------------------------------------------
// disable the instruction cache
//---------------------------------------------------
void 
ARM_ICacheDisable(void);


//---------------------------------------------------
// disable the data cache
//---------------------------------------------------
void 
ARM_DCacheDisable(void);


//---------------------------------------------------
// disable the instruction and data caches
//---------------------------------------------------
void 
ARM_IDCacheDisable(void);


//---------------------------------------------------
// Set the CPU mode to USR
//---------------------------------------------------
void 
ARM_SetCpuUserMode(void);


//---------------------------------------------------
// Set the CPU mode to FIQ
//---------------------------------------------------
void 
ARM_SetCpuFiqMode(void); 


//---------------------------------------------------
// Set the CPU mode to IRQ
//---------------------------------------------------
void 
ARM_SetCpuIrqMode(void);


//---------------------------------------------------
// Set the CPU mode to Supervisor
//---------------------------------------------------
void 
ARM_SetCpuSupervisorMode(void);


//---------------------------------------------------
// Set the CPU mode to Abort
//---------------------------------------------------
void 
ARM_SetCpuAbortMode(void);


//---------------------------------------------------
// Set the CPU mode to Undefined
//---------------------------------------------------
void 
ARM_SetCpuUndefinedMode(void); 


//---------------------------------------------------
// Set the CPU mode to System
//---------------------------------------------------
void 
ARM_SetCpuSystemMode(void); 


//---------------------------------------------------
// establish the CPU privelege mode
//---------------------------------------------------
void 
ARM_SetCpuPrivMode(uint32_t);   // true = priveleged mode


//---------------------------------------------------
// set CPU mode. 
//---------------------------------------------------
void 
ARM_SetCpuMode(unsigned long);          // cpu mode


//---------------------------------------------------
// enable IRQ. CPSR I bit enables IRQ interrupts
// when cleared to 0
//---------------------------------------------------
void 
ARM_EnableIRQ (void);

//---------------------------------------------------
// disable IRQ. CPSR I bit disables IRQ interrupts
// when set to 1, enables when cleared to 0
//---------------------------------------------------
void 
ARM_DisableIRQ (void);

//---------------------------------------------------
// enable FIQ. CPSR F bit enables FIQ interrupts
// when cleared to 0
//---------------------------------------------------
void 
ARM_EnableFIQ (void);

//---------------------------------------------------
// disable FIQ. CPSR F bit disables IRQ interrupts
// when set to 1, enables when cleared to 0
//---------------------------------------------------
void 
ARM_DisableFIQ (void);



#endif