📄 ccxx.c
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/*
*********************************************************************************************************
* cc1100
* inteface functions
*
* File : CCXX.C
* Data : April 12, 2007
*********************************************************************************************************
*/
#include "hal.h"
/*
*********************************************************************************************************
* PROTOTYPES
*********************************************************************************************************
*/
/*
BYTE CcRegs[]= {
GDO_SYNC_END, // IOCFG2 REV | GDO2_INV | GDO2_CFG[5.0]
GDO_HIGH_IMPEDANCE, // IOCFG1 GDO_DS | GDO1_INV | GDO1_CFG[5.0]
GDO_HIGH_IMPEDANCE, // IOCFG0 TEMP_SENSOR_ENABLE | GDO0_INV | GDO0_CFG[5.0]
B0000_0111, // FIFOTHR
0xD3, // SYNC1
0x91, // SYNC0
32, // PKTLEN
B0000_0100, // PKTCTRL1
// PQT[2..0] | WOR_AUTOSYNC | REV | APPEND_STATUS | ADR_CHK[1.0]
// 000 | 0 | 0 | 1 | 01
B0000_0101, // PKTCTRL0
// REV | WHITE_DATA | PKT_FORMAT[1.0] | CC2400_EN | CRC_EN | LENGTH_CONFIG[1.0]
// 0 | 0 | 00 | 0 | 1 | 01
0xF0, // ADDR
0x00, // CHANNR
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x21, // FREQ2 Frequency control word, high byte.
0x35, // FREQ1 Frequency control word, middle byte.
0x2B, // FREQ0 Frequency control word, low byte.
0x7B, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
B0000_0010, // MDMCFG2 Modem configuration.
// DEM_DCFILT_OFF | MOD_FORMAT[2.0] | MANCHESER_EN | SYNC_MODE[2.0]
// 0 | 000 | 0 | 010
B0010_0010, // MDMCFG1 Modem configuration.0x22
// FEC_EN | NUM_PREAMBLE[2.0] | REV2 | CHANSPC[1.0]
// 0 | 010 | 00 | 10
0xF8, // MDMCFG0 Modem configuration.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0x07, // MCSM2
B0001_0000, // MCSM1
// REV2 | CCA_MODE[1.0] | RXOFF_MODE[1.0] | TXOFF_MODE[1.0]
// 00 | 01 | 00 | 00
B0001_1000, // MCSM0 Main Radio Control State Machine configuration.
// REV | FS_AUTOCAL[1.0] |PO_TIMEOUT | PIN_CTRL_EN | XOSC_FORCE_ON
// 0 | 00 | 0 | 0 | 0
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0x87, // WOREVT1
0x6b, // WOREVT0
0xf8, // WORCTRL
0xb6, // FREND1 Front end RX configuration.
B0001_0000, // FREND0 Front end RX configuration.
// REV | LODIV_BUF_CURRENT_TX[1.0] | REV | PA_POWER[2.0]
// 0 | 00 | 0 | 000
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.(38)
0x41, // RCCTRL1
0x00, // RCCTRL0
0x59, // FSTEST
0x7F, // PTEST
0x3F, // AGCTEST
0x88, // TEST2
0x31, // TEST1
0x09 // TEST0
};*/
const char CcRegs[0x2f]= {
0x06, // IOCFG2 Y //0x06
0x2E, // IOCFG1 Y
0x3f, // IOCFG0D Y
0x07, // FIFOTHR Y
0xD3, // SYNC1 Y
0x91, // SYNC0 Y
0xFF, // PKTLEN Y
0x04, // pktctrl1
0x05, // pktctrl0
0x00, // addr Y
0x00, // CHANNR Y
0x0C, // FSCTRL1 Frequency synthesizer control.0X17 0x0c
0x00, // FSCTRL0 Frequency synthesizer control.
0x23, // FREQ2 Frequency control word, high byte.
0x34, // FREQ1 Frequency control word, middle byte.
0x2E, // FREQ0 Frequency control word, low byte.
0xC8, // MDMCFG4 Modem configuration. x2D 0x0e
0x93, // MDMCFG3 Modem configuration.
0x03, // MDMCFG2 Modem configuration.
0x03, // MDMCFG1 Modem configuration.0x22
0xF8, // MDMCFG0 Modem configuration.
0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0x07, // MCSM2
0x00, // MCSM1
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x15, // FOCCFG Frequency Offset Compensation Configuration.
0x6C, // BSCFG Bit synchronization Configuration.
0x83, // AGCCTRL2 AGC control.
0x40, // AGCCTRL1 AGC control.
0x91, // AGCCTRL0 AGC control.
0x87, // WOREVT1
0x6b, // WOREVT0
0xf8, // WORCTRL
0x56, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0xA9, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x0D, // FSCAL0 Frequency synthesizer calibration.(38)
0x41, // RCCTRL1
0x00, // RCCTRL0
0x59, // FSTEST
0x7F, // PTEST
0x3F, // AGCTEST
0x86, // TEST2
0x3D, // TEST1
0x09 // TEST0
};
//-----------------------------------------------------------------------------
// RFnCTRL ->>>
// bit7 BUSY -- 0,idle 1,busy
// bit6 TRRV -- 0,transmit 1,reveive
// bit5 TIMEN --TRRVt 0,disable 1,overtime counter
// bit4 OVER -- 0,runing 1,New data[RERV=1]; Finish sending [RERV=0]
// bit3 INTERR -- unexpectant interrupt
// bit2 TIMERR -- overtime error
// bit1 TRERR -- transmit error
// bit0 RVERR -- receive error :length,crc,pkt
//-----------------------------------------------------------------------------
// RFnSTATUS[0]-> bit7..0,RSII
// RFnSTATUS[1]-> bit7,CRC_OK bit6..0,LQI
//-----------------------------------------------------------------------------
// RFnRxbuf[0] ->length RFnRxbuf[1...]->data
//-----------------------------------------------------------------------------
__no_init char RF0CTRL @LCDM6_;
__no_init char RF0CNT @LCDM7_;
__no_init char RF0ERR @LCDM8_;
char RF0STATUS[2];
//unsigned int *RF0Rxbuf;
char RfTxBuf[22];
char RfRxBuf[22];
char AppRFStatus;
// bit7..6 --
// 00-dile
// 01-busy
// 10-finish
// 11-error
// 000-
// bit6..4 -- rev
// bit3..0 -- plate num
const char PaTable[8] = {0x03,0x0D,0x1C,0x34,0x67,0x60,0x85,0xc3} ;
// | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
// |-30 |-20 |-15 |-10 |-5 | 0 | 5 | 10 | dBm
// BYTE PaTable[8] = {0x00,0x01,0x02,0x34,0x67,0x60,0x85,0xc3} ;
/*
*********************************************************************************************************
* CC_INIT
*
* Description :
* Arguments : none
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
void CC_INIT(void)
{
CC_PowerupResetCCxxxx();
CLR_CSN;
while (READ_MISO); // Wait CCxxxx ready
CC_SPI_bitbang_out(0x00 | CCxxx0_WRITE_BURST); // Send address
for (BYTE i = 0; i < 0x2f; i++)
CC_SPI_bitbang_out(CcRegs[i]); // Send data
SET_CSN;
SpiWriteReg(CCxxx0_PATABLE, PaTable[7]);
RF0CTRL = 0;
RF0ERR = 0;
}
/*
*********************************************************************************************************
* CC_RESET
*
* Description :
* Arguments : none
* Returned Values : none
* Note(s)/Warnings :
*
* <-----40 us----->
* _____ _______________
* CSn | | |
* |__| |______________________
* ____
* MISO____________________________ | |
* |__| |___________
* <----Unknown/don't care-----> ^ ^
* SRES done
*********************************************************************************************************
*/
void CC_PowerupResetCCxxxx(void)
{
SET_CSN;
CC_Wait(3);
CLR_CSN;
CC_Wait(3);
SET_CSN;
CC_Wait(4);
CLR_CSN;
while (READ_MISO);
CC_SPI_bitbang_out(CCxxx0_SRES);
while (READ_MISO);
SET_CSN;
}
/*
*********************************************************************************************************
* CCRSSI
*
* Description : calculate receive siginal strength
* Arguments : rssi register
* Returned Values : signed true strength
* Note(s)/Warnings :
*********************************************************************************************************
*/
#define RSSI_OFSET 76
signed char Cc_RSSI(char Rssi)
{
INT16 tmp;
if(Rssi>=128){
tmp = (Rssi -256)/2 - RSSI_OFSET;
}else{
tmp = (Rssi)/2 - RSSI_OFSET;
}
return (signed char)tmp;
}
/*
*********************************************************************************************************
* CC_SEND
*
* Description :
* Arguments : buf tansmit buffer , the first is buffer length, following actual data
* cnt over time couter prefab value
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
void Cc_Send(char *buf, char cnt)
{
//__disable_interrupt();
KEY_INT_MSK;
SpiStrobe(CCxxx0_SFTX);
SpiWriteBurstReg(CCxxx0_TXFIFO, buf, (*buf)+1);
SpiStrobe(CCxxx0_STX);
RF0CTRL = RF_BUSY | RF_TIMEN;
RF0CNT = cnt; //overtime counter
//__enable_interrupt();
}
/*
*********************************************************************************************************
* CC_RECEIVE
*
* Description :
* Arguments : buf receive buffer
* cnt over time couter prefab value
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
void Cc_Receive(char *buf, char cnt)
{
//__disable_interrupt();
KEY_INT_MSK;
SpiStrobe(CCxxx0_SFRX);
SpiStrobe(CCxxx0_SRX);
*buf = 20;
RF0CTRL = RF_BUSY | RF_TRRV | RF_TIMEN;
RF0CNT = cnt; //overtime counter
//__enable_interrupt();
}
/*
*********************************************************************************************************
* RF_TEST
*
* Description : cc1100 test
* Arguments : none
* Returned Values : none
* Note(s)/Warnings :
*********************************************************************************************************
*/
#ifdef DEBUG
#ifdef DEBUG_RF
void RF_TEST(void)
{
char length;
//waiter id test
Req_Waiter();
Pause_1mS(30);
while(1){
Cc_Receive(RfRxBuf,5);
while(!READ_GDO2);
while(READ_GDO2);
//Pause_1mS(1);
{
if((SpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) {
length = SpiReadReg(CCxxx0_RXFIFO);
if (length <= *RfRxBuf) { //length ok
SET_TEST2; //???????????
*RfRxBuf = length; //get true length
SpiReadBurstReg(CCxxx0_RXFIFO, RfRxBuf+1, length); //read data
SpiReadBurstReg(CCxxx0_RXFIFO, RF0STATUS, 2); //read status
CLR_TEST2; //???????????
}else{ //length error
*RfRxBuf = length;
SpiStrobe(CCxxx0_SIDLE);
RF0CTRL |= RF_RVERR;
}
}else{ //receive error
SpiStrobe(CCxxx0_SIDLE);
RF0CTRL |= RF_RVERR;
}
RF0CTRL |= RF_OVER;
GDO2_INT_MSK; //enable key interrupt
}
//Pause_10uS(70);
Cc_Send(RfTxBuf,3);
Pause_1mS(300);
}
}
#endif
#endif
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