hal.h

1-wire"从机"模拟程序, 不是主机,1-wire的主机模拟程序网上很多.使用mega88模拟DS1990A芯片时序, 再加上模拟主机就可以搭建不使用DALASI芯片而使用1-wire协议的系统.

#ifndef  _HAL_H
#define  _HAL_H

#include <iom88.h>
#include <ina90.h>
#include "common.h"

//----------------------------------------------------------------------------//
//    IO PORT
//----------------------------------------------------------------------------//
#define	  SET_LEDALL 			{PORTC |=  0x0e ;PORTB |=  (1<<PB2);}	
#define	  CLR_LEDALL 			{PORTC &= ~0x0e ;PORTB &= ~(1<<PB2);}

#define   SET_LED4	 			PORTB |=  (1<<PB2)
#define	  CLR_LED4 				PORTB &= ~(1<<PB2)		
#define	  SET_LED3 				PORTC |= 1 << PC3
#define	  CLR_LED3 				PORTC &= ~ (1 << PC3)
#define	  SET_LED2 				PORTC |= 1 << PC2
#define	  CLR_LED2 				PORTC &= ~ (1 << PC2)
#define	  SET_LED1 				PORTC |= 1 << PC1
#define	  CLR_LED1 				PORTC &= ~ (1 << PC1)

#define	  IN_INT0 				(PIND & (1<<PD2))
#define	  IN_INT1 			    (PIND & (1<<PD3))
	


//----------------------------------------------------------------------------//
//    SPI
//----------------------------------------------------------------------------//
#define WRITE_BURST     0x40
#define READ_SINGLE     0x80
#define READ_BURST      0xC0

#define SPI_ENABLE()        SPCR |= 1<<SPE
#define SPI_DISABLE()       SPCR &= ~(1<<SPE)

#define SCLK_DIV2     0x04
#define SCLK_DIV4     0x00
#define SCLK_DIV8     0x05
#define SCLK_DIV16    0x01
#define SCLK_DIV32    0x06
#define SCLK_DIV64    0x02//or 0x07
#define SCLK_DIV128   0x03
// Enble SPI (4-wire Single Master Mode, data centered on first edge of SCK period.
// SCK low in Idle State
#define SPI_INIT_MACRO(freq) \
    do { \
        SPCR = B0101_0000;\
        SPCR = (SPCR&(~0x03))|(freq&0x03); \
        SPSR = (SPSR&(~0x01))|(freq>>2); \
        SPI_ENABLE(); \
    } while (0)

#define SPI_WAIT()  while (!(SPSR&(1<<SPIF)));
//#define SPI_WAIT()  {while (!(SPSR&(1<<SPIF))); OCR2B=SPDR;}

//----------------------------------------------------------------------------//
//    POWER MANAGEMENT
//----------------------------------------------------------------------------//
//SM2 SM1 SM0
//0 0 0 Idle
//0 0 1 ADC Noise Reduction
//0 1 0 Power-down
//0 1 1 Power-save
//1 0 0 Reserved
//1 0 1 Reserved
//1 1 0 Standby(1)
//1 1 1 Reserved
#define  IDLE           0x00
#define  ADCNR          0x02
#define  POWER_DOWN     0x04
#define  POWER_SAVE     0x06
#define  STANDBY        0x0c

//– – – – SM2 SM1 SM0 SE (SMCR)
#define SLEEP_ENABLE()      SMCR |=  1<<SE
#define SLEEP_DISABLE()     SMCR &= ~(1<<SE)
#define SLEEP_MODE_SET(x)   SMCR = x

//----------------------------------------------------------------------------//
//    EEPROM    256-48 512-88 512-168   512/1k/1k
//----------------------------------------------------------------------------//
//EEARL
//EEARH
//EEDR
    //– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
    //0  0    0     0     0     0    0    0    0
    //EECR
//----------------------------------------------------------------------------//
//    ANALOG
//----------------------------------------------------------------------------//
#define ADC_CH0     0x00
#define ADC_CH1     0x01
#define ADC_CH2     0x02
#define ADC_CH3     0x03
#define ADC_CH4     0x04
#define ADC_CH5     0x05
#define ADC_CH6     0x06
#define ADC_CH7     0x07

#define ADC_PS2     0x00  //or 0x01
#define ADC_PS4     0x02
#define ADC_PS8     0x03
#define ADC_PS16    0x04
#define ADC_PS32    0x05
#define ADC_PS64    0x06
#define ADC_PS128   0x07

#define ADC_REF_AREF    0x00
#define ADC_REF_AVCC    0x40
#define ADC_REF_INTER   0xc0

#define ADC_CH_SET(X)   {ADMUX &= 0xE0; ADMUX |=X;}
#define ADC_REF_SET(X)  {ADMUX &= 0x3f; ADMUX |=X;}
#define ADC_PS_SET(X)   {ADCSRA &= 0xf8; ADCSRA |=X;}
#define ADC_START       (ADCSRA |= (1<<ADSC)|(1<<ADIF))
#define ADC_WAIT		{while(ADCSRA &(1<<ADSC));}
#define ADC_OFF			ADCSRA = 0;ADMUX = ADC_CH7 | ADC_REF_INTER | (1<<ADLAR)
#define ADC_REF_DELAY   1

//----------------------------------------------------------------------------//
//    WDT
//----------------------------------------------------------------------------//
#define WDT_16ms	0x00
#define WDT_32ms	0x01
#define WDT_64ms	0x02
#define WDT_0125s	0x03
#define WDT_025s	0x04
#define WDT_05ms	0x05
#define WDT_1s		0x06
#define WDT_2s		0x07
#define WDT_4s		(1<<WDP3)
#define WDT_8s		(1<<WDP3)+(1<<WDP0)



#define TWI_BUSY             0x80
#define TWI_TRRV             0x40
#define TWI_TIMEN            0x20
#define TWI_OVER             0x10
#define TWI_INTERR           0x08
#define TWI_TIMERR           0x04
#define TWI_TRERR            0x02
#define TWI_RVERR            0x01

#endif