dmac.h

U盘控制器USB97C223的固件代码,对2kPAGE NAND FLASH 有很好的支持.

//
// Notes:
//   This is the macro version of dmac_inhibit_tc().
//   It is faster than the function.  Use where performance is critical.
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_inhibit_tc(__chan) { _mcu_register_set_bits(x_bus_req, 0x10 << (__chan)); }

//------------------------------------------------------------------------------
// Name:
//   _dmac_allow_tc
//
// Declaration:
//   void _dmac_allow_tc(uint8 chan);
//
// Purpose:
//   Gates the TC signal for a specific dma channel onto the isa bus.
//   This terminates a multi-session dma transfer by allowing the TC signal
//   to reach the target peripheral.
//
// Arguments:
//   chan - the physical channel number.
//
// Return:
//   None.
//
// Notes:
//   This is the macro version of dmac_allow_tc().
//   It is faster than the function.  Use where performance is critical.
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_allow_tc(__chan) { _mcu_register_clr_bits(x_bus_req, 0x10 << (__chan)); }

//------------------------------------------------------------------------------
// Name:
//   _dmac_force_channel
//
// Declaration:
//   void _dmac_force_channel(uint8 chan);
//
// Purpose:
//   Used to initiate a memory to memory dma transfer.  This is necessary
//   because a "memory target" has no physical dreq signal.
//
// Arguments:
//   chan - the physical channel number.
//
// Return:
//   None.
//
// Notes:
//   This is the macro version of dmac_force_channel().
//   It is faster than the function.  Use where performance is critical.
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_force_channel(__chan) { _dmac_register_wr(_i_dmac_req, kbm_dma_force_dreq |(__chan)); }

//------------------------------------------------------------------------------
// Name:
//   _dmac_load_channel_io
//
// Declaration:
//  void _dmac_load_channel_io(uint8 chan, uint8 ahi, uint8 alo, uint8 chi, uint8 clo, uint8 cmd, uint8 mode);
//
// Purpose:
//   Program a dma channel for a single channel transfer to/from isa io space.
//
// Arguments:
//   chan - the physical channel number.
//   ahi  - high byte of source/target address in isa memory space (e.g, a packet buffer).
//   alo  - low byte of source/target address in isa memory space (e.g, a packet buffer).
//   chi  - high byte of transfer count.
//   clo  - low byte of transfer count.
//   cmd  - the value to load in to the "CH_CMD" (aka _i_dmac_cmd) register.
//   mode - the value to load in to the "CH_MODE" (aka _i_dmac_mode) register.
//
// Return:
//   None.
//
// Notes:
//   Caller must acquire the isa bus and load x_iobase prior to entry.
//
// Notes:
//   This is the macro version of dmac_load_channel_io().
//   It is faster than the function.  Use where performance is critical.
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_load_channel_io(__chan, __ahi, __alo, __chi, __clo, __cmd, __mode) \
{ uint16 offset;                                                                \
  /* clear the flip flop*/                                                      \
  _dmac_register_wr(_i_dmac_byte_ff, 0x00);                                     \
  /* compute the offset to the specified channel's addr/count registers */      \
  offset = k_isaio_window + (2 * __chan);                                       \
  /* plug in the address - depends on iobase reg already loaded */              \
  XBYTE[offset] = __alo;                                                        \
  XBYTE[offset] = __ahi;                                                        \
  /* plug in the length - depends on iobase reg already loaded */               \
  offset++;                                                                     \
  XBYTE[offset] = __clo-1;                                                      \
  XBYTE[offset] = __chi;                                                        \
  /* stuff in the cmd and mode */                                               \
  _dmac_register_wr(_i_dmac_mode, __mode);                                      \
  _dmac_register_wr(_i_dmac_cmd, __cmd);                                        \
}

//------------------------------------------------------------------------------
// Name:
//   _dmac_load_channel_mem
//
// Declaration:
//  void _dmac_load_channel_mem(uint8 sahi, uint8 salo, uint8 dahi, uint8 dalo, uint8 chi, uint8 clo);
//
// Purpose:
//   Program a dma channels 0 and 1 for a dual channel memory to memory transfer.
//
// Arguments:
//   sahi - high byte of source address in isa memory space.
//   salo - low byte of source address in isa memory space.
//   dahi - high byte of destination address in isa memory space.
//   dalo - low byte of destination address in isa memory space.
//   chi  - high byte of transfer count.
//   clo  - low byte of transfer count.
//
// Return:
//   None.
//
// Notes
//   Caller must acquire the isa bus prior to entry.
//   Mem2mem transfers only work with channels 0 and 1.
//   Channel 0 is the source, and channel 1 is the destination.
//
//   This is the macro version of dmac_load_channel_mem().
//   It is faster than the function.  Use where performance is critical.
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_load_channel_mem(__sahi, __salo, __dahi, __dalo, __chi, __clo)    \
{                                                                               \
  /* clear the flip flop*/                                                      \
  _dmac_register_wr(_i_dmac_byte_ff, 0x00);                                     \
  /* plug in the source address - depends on iobase reg already loaded */       \
  _dmac_register_wr(_i_dmac_addr0, __salo);                                     \
  _dmac_register_wr(_i_dmac_addr0, __sahi);                                     \
  /* plug in the destination address - depends on iobase reg already loaded */  \
  _dmac_register_wr(_i_dmac_addr1, __dalo);                                     \
  _dmac_register_wr(_i_dmac_addr1, __dahi);                                     \
  /* plug in the length - depends on iobase reg already loaded */               \
  _dmac_register_wr(_i_dmac_cnt1, __clo-1);                                     \
  _dmac_register_wr(_i_dmac_cnt1, __chi);                                       \
  /* set the mode, both channels */                                             \
  _dmac_register_wr(_i_dmac_mode, kbm_dma_block_mode |kbm_dma_read_xfer |kbm_dma_ch0);  \
  _dmac_register_wr(_i_dmac_mode, kbm_dma_block_mode |kbm_dma_write_xfer |kbm_dma_ch1); \
  /* set for mem2mem */                                                         \
  _dmac_register_wr(_i_dmac_cmd, kbm_dma_mem2mem);                              \
}

//------------------------------------------------------------------------------
// Name:
//   _dmac_initiate_transfer
//
// Declaration:
//  void _dmac_initiate_transfer(uint8 pchan, uint16 isaaddr, uint8 cmd, uint8 mode, t_bool final);
//
// Purpose:
//   Initiates the proper transfer type based on the cmd and mode.
//
// Arguments:
//   pchan     - the physical dma channel.  ignored for mem2mem transfers.
//   isaaddr   - the source or target isa address (memory or io).
//   pktaddrhi - hi byte of packet buffer address in isa memory.
//   pktlenlo  - lo byte of packet length (always 64 or less since its a '102)
//   cmd       - the value for the 8237a dmac's command register.
//   mode      - the value for the 8237a dmac's mode register.
//   final     - if k_true means to gate tc onto the isa bus.
//
// Return:
//   None.
//
// Notes:
//   This is a macro to try and speed up the udp interface manager for u2dp.
//   That is the only reason this isn't a function.
//
//   This is the macro version of dmac_initiate_transfer().
//   It is faster than the function.  Use where performance is critical.
//
//
// Since:
//   MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_initiate_transfer(__pchan, __isaaddr, __pktaddrhi, __pktlenlo, __cmd, __mode, __final) \
{                                                                              \
  trace0(0, udp, 0, "_dmac_initiate_transfer()");                            \
  if ((__cmd) & kbm_dma_mem2mem)                                               \
    if ((__mode) & kbm_dma_read_xfer)                                          \
      dmac_initiate_pkt2isa_transfer((__isaaddr), (__pktaddrhi), (__pktlenlo));\
    else                                                                       \
      dmac_initiate_isa2pkt_transfer((__isaaddr), (__pktaddrhi), (__pktlenlo));\
  else                                                                         \
    dmac_initiate_io_transfer((__pchan), (__pktaddrhi), (__pktlenlo), (__cmd), (__mode), (__final)); \
}

//------------------------------------------------------------------------------
// prototypes
void dmac_clr_alltc(void) reentrant;
void dmac_disable_channel(uint8 chan) reentrant;
void dmac_enable_channel(uint8 chan) reentrant;
void dmac_inhibit_tc(uint8 chan) reentrant;
void dmac_allow_tc(uint8 chan) reentrant;
void dmac_force_channel(uint8 chan) reentrant;
void dmac_load_channel_io(uint8 chan, uint8 ahi, uint8 alo, uint8 chi, uint8 clo, uint8 cmd, uint8 mode) reentrant;
void dmac_load_channel_mem(uint8 sahi, uint8 salo, uint8 dahi, uint8 dalo, uint8 chi, uint8 clo) reentrant;
void dmac_initiate_pkt2isa_transfer(uint16 memaddr, uint8 pktaddrhi, uint8 pktlenlo) reentrant;
void dmac_initiate_isa2pkt_transfer(uint16 memaddr, uint8 pktaddrhi, uint8 pktlenlo) reentrant;
void dmac_initiate_io_transfer(uint8 pchan, uint8 pktaddrhi, uint8 pktlenlo, uint8 cmd, uint8 mode, t_bool final_burst) reentrant;

//---eof------------------------------------------------------------------------