📄 dmac.h
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/*============================================================================
____________________________________________________________________________
______________________________________________
SSSS M M CCCC Standard Microsystems Corporation
S MM MM SSSS C Austin Design Center
SSS M M M S C 11000 N. Mopac Expressway
S M M SSS C Stonelake Bldg. 6, Suite 500
SSSS M M S CCCC Austin, Texas 78759
SSSS ______________________________________________
____________________________________________________________________________
Copyright(C) 1999, Standard Microsystems Corporation
All Rights Reserved.
This program code listing is proprietary to SMSC and may not be copied,
distributed, or used without a license to do so. Such license may have
Limited or Restricted Rights. Please refer to the license for further
clarification.
____________________________________________________________________________
Notice: The program contained in this listing is a proprietary trade
secret of SMSC, Hauppauge, New York, and is copyrighted
under the United States Copyright Act of 1976 as an unpublished work,
pursuant to Section 104 and Section 408 of Title XVII of the United
States code. Unauthorized copying, adaption, distribution, use, or
display is prohibited by this law.
____________________________________________________________________________
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph(c)(1)(ii) of the Rights
in Technical Data and Computer Software clause at DFARS 52.227-7013.
Contractor/Manufacturer is Standard Microsystems Corporation,
80 Arkay Drive, Hauppauge, New York, 1178-8847.
____________________________________________________________________________
____________________________________________________________________________
<module name> - <module description>
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comments tbd
____________________________________________________________________________
Revision History
Date Who Comment
________ ___ _____________________________________________________________
07/16/99 tbh -initial version
07/27/01 tbh -assimilated sgdmac_initiate_pkt2isa_transfer,
sgdmac_initiate_isa2pkt_transfer, and sgdmac_initiate_io_transfer
from the udp interface manager for the u2dp project.
============================================================================*/
//------------------------------------------------------------------------------
// dmac registers
// these are special case mcu registers that exist in isa io space
// they are handled differently from standard isa registers for performance
typedef code uint16 t_dmac_register;
#define _i_dmac_addr0 0x4000 // rw channel 0 current address
#define _i_dmac_cnt0 0x4001 // rw channel 0 byte count
#define _i_dmac_addr1 0x4002 // rw channel 1 current address
#define _i_dmac_cnt1 0x4003 // rw channel 1 byte count
#define _i_dmac_addr2 0x4004 // rw channel 2 current address
#define _i_dmac_cnt2 0x4005 // rw channel 2 byte count
#define _i_dmac_addr3 0x4006 // rw channel 3 current address
#define _i_dmac_cnt3 0x4007 // rw channel 3 byte count
#define _i_dmac_sts 0x4008 // r channel status register
#define _i_dmac_cmd 0x4008 // W command register
#define _i_dmac_req 0x4009 // W write request register
#define _i_dmac_mask 0x400A // rw write single mask register
#define _i_dmac_mode 0x400B // W write mode register
#define _i_dmac_byte_ff 0x400C // W clear byte pointer flip flop
#define _i_dmac_rd_temp 0x400D // r read temporary register
#define _i_dmac_mstr_clr 0x400D // W master clear register
#define _i_dmac_clr_mask 0x400E // W clear mask register
#define _i_dmac_all_mask 0x400F // W write all mask Bits register
//+-----------------------------------------------------------------------------
// Name:
// _dmac_register_rd
//
// Declaration:
// t_datum _dmac_register_rd(t_dmac_register reg);
//
// Purpose:
// Read a datum from one of the dmac registers.
//
// Arguments:
// reg - the t_dmac_register to be read.
//
// Return:
// The t_datum stored at the register location.
//
// Notes:
// 10x only. The 20x family does not have an 8237a compatible dmac.
//
// Since:
// MinimOS 2.1
//------------------------------------------------------------------------------
#define _dmac_register_rd(__ireg) (XBYTE[(__ireg)])
//+-----------------------------------------------------------------------------
// Name:
// _dmac_register_wr
//
// Declaration:
// void _dmac_register_wr(t_dmac_register reg, t_datum datum);
//
// Purpose:
// Write a datum to one of the dmac registers.
//
// Arguments:
// reg - the t_dmac_register to be written.
// datum - the t_datum to write to it.
//
// Return:
// None.
//
// Notes:
// 10x only. The 20x family does not have an 8237a compatible dmac.
//
// Since:
// MinimOS 2.1
//------------------------------------------------------------------------------
#define _dmac_register_wr(__ireg, __datum) { XBYTE[(__ireg)] = (__datum); }
//------------------------------------------------------------------------------
// IMPORTANT NOTE:
// The macro versions of the functions are faster, but trickier to use properly.
// they exist only to improve the performance of the kernel. If you personally
// choose to use the macro versions (to squeeze out every ounce of performance)
// then you should make sure you understand any differences between the macros
// and the functions, and how that can affect your implementation.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Name:
// _dmac_clr_alltc
//
// Declaration:
// void _dmac_clr_alltc(void);
//
// Purpose:
// Clears all pending TCs form the "CH_STS" register of the 8237a by reading
// the clear-on-read channel status register.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is the macro version of dmac_clr_alltc().
// It is faster than the function. Use where performance is critical.
//
// Since:
// MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_clr_alltc() { uint8 tmp = _dmac_register_rd(_i_dmac_sts); }
//------------------------------------------------------------------------------
// Name:
// _dmac_disable_channel
//
// Declaration:
// void _dmac_disable_channel(uint8 chan);
//
// Purpose:
// Disable a dma channel so it can be configured for a transfer.
//
// Arguments:
// chan - the physical channel number to disable.
//
// Return:
// None.
//
// Notes:
// This is the macro version of dmac_disable_channel().
// It is faster than the function. Use where performance is critical.
//
// Since:
// MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_disable_channel(__chan) { _dmac_register_wr(_i_dmac_mask, kbm_dma_msk_ch |(__chan)); }
//------------------------------------------------------------------------------
// Name:
// _dmac_enable_channel
//
// Declaration:
// void _dmac_enable_channel(uint8 chan);
//
// Purpose:
// Enable a dma channel so it can perform a transfer.
//
// Arguments:
// chan - the physical channel number to enable.
//
// Return:
// None.
//
// Notes:
// This is the macro version of dmac_enable_channel().
// It is faster than the function. Use where performance is critical.
//
// Since:
// MinimOS-2.1
//------------------------------------------------------------------------------
#define _dmac_enable_channel(__chan) { _dmac_register_wr(_i_dmac_mask, (__chan)); \
_mcu_register_clr_bits(x_bus_msk, 1 << (__chan)); }
//------------------------------------------------------------------------------
// Name:
// _dmac_inhibit_tc
//
// Declaration:
// void _dmac_inhibit_tc(uint8 chan);
//
// Purpose:
// Gates the TC signal for a specific dma channel off of the isa bus.
// This allows multiple dma sessions to run without allowing the
// target peripheral to see the TC signal.
//
// Arguments:
// chan - the physical channel number.
//
// Return:
// None.
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