📄 mcu.h
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//
//------------------------------------------------------------------------------
#ifdef k_20x_family
//------------------------------------------------------------------------------
#define k_max_pnr 6
#define kbm_pnr 0x07
#define k_max_txfifo 3 // emulated
#define k_max_gpfifo 0
//------------------------------------------------------------------------------
// the 200 does not have an isa bus
#define k_isaio_window 0x0000
#define k_isamem_window 0x0000
//------------------------------------------------------------------------------
// the base address of each packet buffer
extern uint8 code k_pkt_addrlo[];
extern uint8 code k_pkt_addrhi[];
//------------------------------------------------------------------------------
// mcu registers and bit definitions
t_mcu_register x_isr0 at_mcu(80); // r source regster external0
t_mcu_register x_imr0 at_mcu(93); // rw mask regster
// x_isr0/x_imr0 bits
#define kbm_isr0_usb_stat 0x80 // r/rw
#define kbm_isr0_setup 0x40 // r/rw
#define kbm_isr0_fdc_irq 0x20 // r/rw
#define kbm_isr0_blk_xfer_complete 0x20 // r/rw -> 210
#define kbm_isr0_ata_irq 0x10 // r/rw
#define kbm_isr0_fmc_irq 0x10 // r/rw -> 210
#define kbm_isr0_ramrd_b 0x08 // r/rw
#define kbm_isr0_ramrd_a 0x04 // r/rw
#define kbm_isr0_ramwr_b 0x02 // r/rw
#define kbm_isr0_ramwr_a 0x01 // r/rw
//------------------------------------------------------------------------------
t_mcu_register x_usb_stat at_mcu(AB); // rw usb bus status regster
t_mcu_register x_usb_msk at_mcu(AC); // rw usb bus status mask regster
// x_usb_stat/x_usb_msk bits
#define kbm_usb_stat_ep2_err 0x40 // rw/rw
#define kbm_usb_stat_2dot0 0x20 // rw/rw
#define kbm_usb_stat_resume 0x10 // rw/rw
#define kbm_usb_stat_reset 0x08 // rw/rw
#define kbm_usb_stat_error 0x04 // rw/rw
//------------------------------------------------------------------------------
t_mcu_register x_usb_err at_mcu(DA); // r usb error register
// x_usb_err bits
#define kbm_usberr_to 0x80 // rw
#define kbm_usberr_token 0x40 // rw
#define kbm_usberr_ovrflw 0x20 // rw
#define kbm_usberr_stall 0x10 // rw
#define kbm_usberr_dtog 0x08 // rw
#define kbm_usberr_bitstf 0x04 // rw
#define kbm_usberr_pid 0x02 // rw
#define kbm_usberr_crc 0x01 // rw
//------------------------------------------------------------------------------
t_mcu_register x_isr1 at_mcu(90); // r source regster external1
t_mcu_register x_imr1 at_mcu(94); // rw mask regster
// x_isr1/x_imr1 bits
#define kbm_isr1_ep0zlp 0x80 // r/rw
#define kbm_isr1_debug 0x40 // r/rw
#define kbm_isr1_ata_pio 0x20 // r
#define kbm_isr1_ep1rx 0x10 // r/rw
#define kbm_isr1_ep1tx 0x08 // r/rw
#define kbm_isr1_ep0rx 0x04 // r/rw
#define kbm_isr1_ep0tx 0x02 // r/rw
#define kbm_isr1_suspend 0x01 // r/rw
//------------------------------------------------------------------------------
t_mcu_register x_sie_stat at_mcu(B0); // rw sie status regster external3
t_mcu_register x_sie_msk at_mcu(AE); // rw sie status mask regster
// x_sie_stat/x_sie_msk bits
#define kbm_sie_stat_set_stall 0x80 // rw/rw
#define kbm_sie_stat_clr_stall 0x40 // rw/rw
#define kbm_sie_stat_set_cfg 0x20 // rw/rw
//#define kbm_sie_stat_get_cfg 0x10 // rw/rw
#define kbm_sie_stat_set_ifc 0x08 // rw/rw
//#define kbm_sie_stat_get_ifc 0x04 // rw/rw
#define kbm_sie_stat_set_rwu 0x02 // rw/rw
#define kbm_sie_stat_clr_rwu 0x01 // rw/rw
//------------------------------------------------------------------------------
t_mcu_register x_chip_rev at_mcu(95); // r device revision regster
t_mcu_register x_chip_id at_mcu(96); // r device id regster
//------------------------------------------------------------------------------
t_mcu_register x_gpioa_dir at_mcu(97); // rw gpio configuration regster
t_mcu_register x_gpioa_out at_mcu(9A); // rw gpio data Output regster
t_mcu_register x_gpioa_in at_mcu(9B); // r gpio data Input regster
t_mcu_register x_isr_gpio at_mcu(C0); // rw gpio source regster external4
t_mcu_register x_imr_gpio at_mcu(9C); // rw gpio mask regster
// x_gpioa_dir/x_gpioa_out/x_gpioa_in/x_isr_gpio/x_imr_gpio bits
#define kbm_gpio7 0x80 // rw/rw/r/rw/rw
#define kbm_gpio6 0x40 // rw/rw/r/rw/rw
#define kbm_gpio5 0x20 // rw/rw/r/rw/rw
#define kbm_gpio4 0x10 // rw/rw/r/rw/rw
#define kbm_gpio_sof 0x10 // rw/rw/r/rw/rw
#define kbm_gpio3 0x08 // rw/rw/r/rw/rw
#define kbm_gpio_t1 0x08 // rw/rw/r/rw/rw
#define kbm_gpio2 0x04 // rw/rw/r/rw/rw
#define kbm_gpio_t0 0x04 // rw/rw/r/rw/rw
#define kbm_gpio1 0x02 // rw/rw/r/rw/rw
#define kbm_gpio_txd 0x02 // rw/rw/r/rw/rw
#define kbm_gpio0 0x01 // rw/rw/r/rw/rw
#define kbm_gpio_rxd 0x01 // rw/rw/r/rw/rw
//------------------------------------------------------------------------------
t_mcu_register x_isr_nak at_mcu(D7); // rw nak source register external5
t_mcu_register x_imr_nak at_mcu(D9); // rw nak mask register
// x_isr_nak/x_imr_nak bits
#define kbm_nyet2rx 0x80 // rw/rw
#define kbm_nyet0rx 0x40 // rw/rw
#define kbm_nak2tx 0x20 // rw/rw
#define kbm_nak2rx 0x10 // rw/rw
#define kbm_nak1tx 0x08 // rw/rw
#define kbm_nak1rx 0x04 // rw/rw
#define kbm_nak0tx 0x02 // rw/rw
#define kbm_nak0rx 0x01 // rw/rw
//------------------------------------------------------------------------------
t_mcu_register x_util_config at_mcu(9D); // rw misc Configuration regster
//extern t_mcu_register x_util_config; // rw misc Configuration regster
// x_util_config bits
#define kbm_util_config_sram_sw 0x80 // rw
// for the 201, a sadly unimplemented bit
#define kbm_util_config_debug_enb 0x40 // rw
// for the 210
#define kbm_util_config_dev_reset 0x40 // rw
#define kbm_util_config_sof 0x10 // rw
#define kbm_util_config_t1 0x08 // rw
#define kbm_util_config_t0 0x04 // rw
#define kbm_util_config_rxd 0x02 // rw
#define kbm_util_config_txd 0x01 // rw
//------------------------------------------------------------------------------
t_mcu_register x_debug at_mcu(9E); // rw debug data output register
t_mcu_register x_sram_data at_mcu(9F); // rw sram data port register
t_mcu_register x_sram_addr_lo at_mcu(A1); // rw sram address lo register
t_mcu_register x_sram_addr_hi at_mcu(A2); // rw sram address hi register
//------------------------------------------------------------------------------
t_mcu_register x_mcutest2 at_mcu(A3); // rw reserved for test
t_mcu_register x_mcutest1 at_mcu(A4); // rw reserved for test
//------------------------------------------------------------------------------
t_mcu_register x_clock_sel at_mcu(A5); // rw 8051 clock selelect regster
// x_clock_sel bits
#define kbm_clksel_sleep 0x80 // rw
#define kbm_clksel_rosc_en 0x40 // rw
#define kbm_clksel_mcuclk_src 0x20 // rw
#ifdef k_mcu_97201
#define kbm_clksel_clk_valid 0x04 // r // sneaked in to the 201 $$$rcc
#endif
#ifdef k_flash_family
#define kbm_clksel_clk_valid 0x10 // r
#endif
#if defined(k_mcu_97223) ||defined(k_mcu_97226)
#define kbm_clksel_mcu_clk_1dot875_mhz 0x00 //rw // [3:2] mcu_clk bits for 223
#define kbm_clksel_mcu_clk_3dot75_mhz 0x04 //rw
#define kbm_clksel_mcu_clk_30dot0_mhz 0x2c //rw //also set mcuclk_src bit
#else
#define kbm_clksel_mcu_clk_3dot75_mhz 0x00 // rw
#define kbm_clksel_mcu_clk_7dot50_mhz 0x08 // rw
#define kbm_clksel_mcu_clk_15dot0_mhz 0x10 // rw
#define kbm_clksel_mcu_clk_30dot0_mhz 0x18 // rw
#endif
//------------------------------------------------------------------------------
t_mcu_register x_usb_addr at_mcu(A9); // rw sie address regster
// x_sie_addr bits
#define kbm_sie_addr_enb 0x80; // rw
//------------------------------------------------------------------------------
t_mcu_register x_sie_conf at_mcu(AA); // rw sie configuration regster
// x_sie_conf bits
//#define kbm_sie_conf_setup_dly 0x80 // rw obsolete 01/23/01 tbh
#define kbm_sie_conf_bus_pwr_en 0x80 // rw added 7/01/03 for 223 pjc
#define kbm_sie_conf_disconnect 0x40 // rw updated 5/31/01 cds
#define kbm_sie_conf_en_extframe 0x40 // rw
#define kbm_sie_conf_ext_phy 0x08 // rw
#define kbm_sie_conf_hspeed 0x04 // rw
#define kbm_sie_conf_resume 0x02 // rw
#define kbm_sie_conf_suspend 0x01 // rw
//------------------------------------------------------------------------------
t_mcu_register x_usb_conf at_mcu(AD); // r USB configuration
//------------------------------------------------------------------------------
t_mcu_register x_ep0rx_ctl at_mcu(AF); // rw endpoint 0 receive control regster
t_mcu_register x_ep0tx_ctl at_mcu(B1); // rw endpoint 0 transmit control regster
t_mcu_register x_ep1rx_ctl at_mcu(B2); // rw endpoint 1 receive control regster
t_mcu_register x_ep1tx_ctl at_mcu(B3); // rw endpoint 1 transmit control regster
// x_ep0tx_ctl/x_ep1tx_ctl bits
#define kbm_epctltx_tx 0x10 // rw
#define kbm_epctltx_stall 0x04 // rw
#define kbm_epctltx_enable 0x01 // rw
// x_ep0rx_ctl/x_ep1rx_ctl bits
#define kbm_epctlrx_dtog 0x08 // r
#define kbm_epctlrx_stall 0x04 // rw
#define kbm_epctlrx_enable 0x01 // rw
//------------------------------------------------------------------------------
t_mcu_register x_ep2_ctl at_mcu(B4); // rw
// x_ep2_ctl bits
#define kbm_ep2_ctl_dir 0x80 // rw
#define kbm_ep2_ctl_wrtog_valid 0x40 // rw
#define kbm_ep2_ctl_ramwr_tog 0x20 // rw
#define kbm_ep2_ctl_ramrd_tog 0x10 // rw
#define kbm_ep2_ctl_rx_stall 0x08 // rw
#define kbm_ep2_ctl_tx_stall 0x04 // rw
#define kbm_ep2_ctl_rdtog_valid 0x02 // rw
#define kbm_ep2_ctl_enable 0x01 // rw
//------------------------------------------------------------------------------
t_mcu_register x_ep0rx_bc at_mcu(B5); // rw endpoint 0 receive byte count
t_mcu_register x_ep0tx_bc at_mcu(B6); // rw endpoint 0 transmit byte count
t_mcu_register x_ep1rx_bc at_mcu(B7); // rw endpoint 1 receive byte count
t_mcu_register x_ep1tx_bc at_mcu(C7); // rw endpoint 1 transmit byte count
//x_ep0rx_bc/x_ep0tx_bc/x_ep1rx_bc/x_ep1tx_bc bits
#define kbm_epbc_64byte 0x40 // rw/rw/rw/rw
#define kbm_epbc_mask 0x3F // rw/rw/rw/rw
//------------------------------------------------------------------------------
t_mcu_register x_ramwrbc_a1 at_mcu(CE); // rw ram buffer write byte count register a1
t_mcu_register x_ramrdbc_a1 at_mcu(D3); // rw ram buffer read byte count register a1
t_mcu_register x_ramwrbc_b1 at_mcu(D1); // rw ram buffer write byte count register b1
t_mcu_register x_ramrdbc_b1 at_mcu(D5); // rw ram buffer read byte count register b1
t_mcu_register x_ramwrbc_a2 at_mcu(CF); // rw ram buffer write byte count register a2
t_mcu_register x_ramrdbc_a2 at_mcu(D4); // rw ram buffer read byte count register a2
t_mcu_register x_ramwrbc_b2 at_mcu(D2); // rw ram buffer write byte count register b2
t_mcu_register x_ramrdbc_b2 at_mcu(D6); // rw ram buffer read byte count register b2
// x_ramwr_a1/x_ramrd_a1/x_ramwr_b1/x_ramrd_b1 bits
#define kbm_ramrdwr_512bytes 0x02 // rw/rw/rw/rw
#define kbm_ramrdwr_count8 0x01 // rw/rw/rw/rw
//------------------------------------------------------------------------------
#if defined(k_mcu_97200) || defined(k_mcu_97201)
// isolate some registers that only exist on the 9720X
t_mcu_register x_msb_ata at_mcu(DB); // rw msb at_mcua control status data register
t_mcu_register x_lsb_ata at_mcu(DC); // rw lsb at_mcua control status data register
t_mcu_register x_ata_ctl at_mcu(DD); // rw
// x_ata_ctl bits
#define kbm_ata_ctl_out_control 0x80 // rw
#define kbm_ata_ctl_pio_cmpl 0x40 // rw
#define kbm_ata_ctl_ata_abort 0x20 // rw
#define kbm_ata_ctl_ata_error 0x10 // rw
#define kbm_ata_ctl_auto_tog 0x08 // rw
#define kbm_ata_ctl_auto_trans 0x04 // rw
#define kbm_ata_ctl_muxen 0x02 // rw
#define kbm_ata_ctl_udma_enb 0x01 // rw
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