mcu.h

U盘控制器USB97C223的固件代码,对2kPAGE NAND FLASH 有很好的支持.

t_isa_register i_dma_cnt3            at_isa(0x0007);  // rw   channel 3 byte count
t_isa_register i_dma_sts             at_isa(0x0008);  // r    channel status register
t_isa_register i_dma_cmd             at_isa(0x0008);  // W    command register
// i_dma_sta bits (aka ch_stat, same bits as x_bus_stat/x_bus_msk)
// i_dma_cmd bits (aka ch_cmd)
#define kbm_dma_dack_sens            0x80      // W
#define kbm_dma_dreq_sens            0x40      // W
#define kbm_dma_write_time           0x20      // W
#define kbm_dma_priority             0x10      // W
#define kbm_dma_comp_time            0x08      // W
#define kbm_dma_ctrl_enable          0x04      // W
#define kbm_dma_addr_hold            0x02      // W
#define kbm_dma_mem2mem              0x01      // W

//------------------------------------------------------------------------------
t_isa_register i_dma_req             at_isa(0x0009);  // W    write request register
t_isa_register i_dma_mask            at_isa(0x000A);  // rw   write single mask register
// i_dma_req/i_dma_mask bits (aka ch_req/ch_mask)
#define kbm_dma_msk_ch               0x04      // W    the channel mask bit in mask register
#define kbm_dma_ch_msk               0x03      // W    the mask to read the channel fron the mode/mask/req registers
#define kbm_dma_force_dreq           0x04      // W    the force dreq bit in req register

//------------------------------------------------------------------------------
t_isa_register i_dma_mode            at_isa(0x000B);  // W    write mode register
//extern t_isa_register i_dma_mode;                 // W    write mode register
// i_dma_mode bits
#define kbm_dma_mode_mode1           0x80      // W
#define kbm_dma_mode_mode0           0x40      // W
#define kbm_dma_mode_inc_dec         0x20      // W
#define kbm_dma_mode_auto_init       0x10      // W
#define kbm_dma_mode_rwv1            0x08      // W
#define kbm_dma_mode_rwv0            0x04      // W
#define kbm_dma_mode_sel1            0x02      // W
#define kbm_dma_mode_sel0            0x01      // W
// mode[1:0); bit field
#define kbm_dma_cascade_mode         0xC0      // W
#define kbm_dma_block_mode           0x80      // W
#define kbm_dma_single_mode          0x40      // W
#define kbm_dma_demand_mode          0x00      // W
// rwv[1:0); bit field
#define kbm_dma_read_xfer            0x08      // W
#define kbm_dma_write_xfer           0x04      // W
#define kbm_dma_verify_xfer          0x00      // W
// i_dma_mode/i_dma_req/i_dma_mask bits (aka ch_mode/ch_req/ch_mask)
#define kbm_dma_ch3                  0x03      // W
#define kbm_dma_ch2                  0x02      // W
#define kbm_dma_ch1                  0x01      // W
#define kbm_dma_ch0                  0x00      // W

//------------------------------------------------------------------------------
t_isa_register i_dma_byte_ff         at_isa(0x000C);  // W    clear byte pointer flip flop
t_isa_register i_dma_rd_temp         at_isa(0x000D);  // r    read temporary register
t_isa_register i_dma_mstr_clr        at_isa(0x000D);  // W    master clear register
t_isa_register i_dma_clr_mask        at_isa(0x000E);  // W    clear mask register
t_isa_register i_dma_all_mask        at_isa(0x000F);  // W    write all mask Bits register
// i_dma_all_mask bits
#define kbm_dma_ch3_msk              0x08      // W
#define kbm_dma_ch2_msk              0x04      // W
#define kbm_dma_ch1_msk              0x02      // W
#define kbm_dma_ch0_msk              0x01      // W

//-------------------------------------------------------------------------v-v-v
#if defined(k_mcu_97102) || defined(k_mcu_97FDC)
// nothing from here down is present on the '100

#if defined(k_mcu_97102)
// the 102 has a hub
t_mcu_register x_hub_id_vendorl      at_mcu(7FA0);  // rw  vendor ID low byte
t_mcu_register x_hub_id_vendorh      at_mcu(7FA1);  // rw  vendor ID high byte
t_mcu_register x_hub_id_productl     at_mcu(7FA2);  // rw  product ID low byte
t_mcu_register x_hub_id_producth     at_mcu(7FA3);  // rw  product ID high byte
t_mcu_register x_hub_bcd_devicel     at_mcu(7FA4);  // rw  usb device release number low
t_mcu_register x_hub_bcd_deviceh     at_mcu(7FA5);  // rw  usb device release number high
t_mcu_register x_hub_ctrl1           at_mcu(7FA6);  // rw  hub control register 1
// x_hub_ctrl1 bits
#define kbm_hub_ctrl1_nreset         0x80      // rw
#define kbm_hub_ctrl1_bypass5        0x20      // rw
#define kbm_hub_ctrl1_bypass4        0x10      // rw
#define kbm_hub_ctrl1_bypass3        0x08      // rw
#define kbm_hub_ctrl1_bypass2        0x04      // rw
#define kbm_hub_ctrl1_force_se0      0x02      // rw
#define kbm_hub_ctrl1_gang_pwr       0x01      // rw
//-------------------------------------------------------------------------^-^-^
t_mcu_register x_hub_ctrl2           at_mcu(7FA7);  // rw  hub control register 2
// x_hub_ctrl2 bits
#define kbm_hub_ctrl2_extcvr4        0x10      // rw
#define kbm_hub_ctrl2_extcvr3        0x08      // rw
#define kbm_hub_ctrl2_extcvr2        0x04      // rw

//------------------------------------------------------------------------------
t_mcu_register x_epcmd               at_mcu(7FAA);
t_mcu_register x_non_ctrl_eph        at_mcu(7FAB);  // 0 = control, 1 = non-control
t_mcu_register x_non_ctrl_epl        at_mcu(7FAC);
t_mcu_register x_rxhdrfifo           at_mcu(7FAD);
t_mcu_register x_mmpcmd              at_mcu(7FAE);
t_mcu_register x_mmpstate            at_mcu(7FAF);
#endif

#if defined(k_mcu_97FDC)
// these registers are at_mcu a different address on the fdc
t_mcu_register x_epcmd               at_mcu(7FA0);
t_mcu_register x_non_ctrl_eph        at_mcu(7FA1);  // 0 = control, 1 = non-control
t_mcu_register x_non_ctrl_epl        at_mcu(7FA2);
t_mcu_register x_rxhdrfifo           at_mcu(7FA3);
t_mcu_register x_mmpcmd              at_mcu(7FA4);
t_mcu_register x_mmpstate            at_mcu(7FA5);
#endif

// x_epcmd bits
// e.g., x_epcmd = kbm_epcmd_tx | kbm_epcmd_stall | ndp;
#define kbm_epcmd_tx                 0x80
#define kbm_epcmd_rx                 0x00
#define kbm_epcmd_disable            0x00
#define kbm_epcmd_stall              0x10
#define kbm_epcmd_enable             0x20
#define kbm_epcmd_busy               0x30
#define kbm_epcmd_clrtog             0x40
#define kbm_epcmd_settog             0x50
#define kbm_epcmd_clriso             0x60
#define kbm_epcmd_setiso             0x70
// x_mmpcmd commands
// e.g., x_mmpcmd = kbm_mmp_enable | ndp;
#define kbm_mmp_disable              0x00
#define kbm_mmp_enable               0x20
#define kbm_mmp_decr                 0x40
#define kbm_mmp_incr                 0x60
#define kbm_mmp_getstate             0x80
#define kbm_mmp_rst_dsb              0xE0
// x_mmpstate bits
// e.g., x_mmpstate = kbm_mmp_decr | ndp;
#define kbm_mmp_enabled              0x80
#define kbm_mmp_count_msk            0x1F

//------------------------------------------------------------------------------
t_mcu_register x_innakl              at_mcu(7FEC);
t_mcu_register x_innakh              at_mcu(7FED);
t_mcu_register x_outnakl             at_mcu(7FEE);
t_mcu_register x_outnakh             at_mcu(7FEF);

//------------------------------------------------------------------------------
t_mcu_register x_txfifo_count0       at_mcu(7F40);
t_mcu_register x_txfifo_count1       at_mcu(7F41);
t_mcu_register x_txfifo_count2       at_mcu(7F42);
t_mcu_register x_txfifo_count3       at_mcu(7F43);
t_mcu_register x_txfifo_count4       at_mcu(7F44);
t_mcu_register x_txfifo_count5       at_mcu(7F45);
t_mcu_register x_txfifo_count6       at_mcu(7F46);
t_mcu_register x_txfifo_count7       at_mcu(7F47);
t_mcu_register x_txfifo_count8       at_mcu(7F48);
t_mcu_register x_txfifo_count9       at_mcu(7F49);
t_mcu_register x_txfifo_count10      at_mcu(7F4A);
t_mcu_register x_txfifo_count11      at_mcu(7F4B);
t_mcu_register x_txfifo_count12      at_mcu(7F4C);
t_mcu_register x_txfifo_count13      at_mcu(7F4D);
t_mcu_register x_txfifo_count14      at_mcu(7F4E);
t_mcu_register x_txfifo_count15      at_mcu(7F4F);

//------------------------------------------------------------------------------
#define k_sgdma_baseaddr             0x7FB0
#define k_sgdma_register_interleave  10
#define k_sgdma_offset_start_fifo    0
#define k_sgdma_offset_done_fifo     1
#define k_sgdma_offset_adhi          2
#define k_sgdma_offset_adlo          3
#define k_sgdma_offset_szhi          4
#define k_sgdma_offset_szlo          5
#define k_sgdma_offset_total_pkts    6
#define k_sgdma_offset_done_pkts     7
#define k_sgdma_offset_sts           8
#define k_sgdma_offset_cmd           9

//------------------------------------------------------------------------------
t_mcu_register x_sgdma_start_fifo0   at_mcu(7FB0);  // rw
t_mcu_register x_sgdma_done_fifo0    at_mcu(7FB1);  // rw
t_mcu_register x_sgdma_adhi0         at_mcu(7FB2);
t_mcu_register x_sgdma_adlo0         at_mcu(7FB3);
t_mcu_register x_sgdma_szhi0         at_mcu(7FB4);
t_mcu_register x_sgdma_szlo0         at_mcu(7FB5);
t_mcu_register x_sgdma_total_pkts0   at_mcu(7FB6);
t_mcu_register x_sgdma_done_pkts0    at_mcu(7FB7);
t_mcu_register x_sgdma_sts0          at_mcu(7FB8);
t_mcu_register x_sgdma_cmd0          at_mcu(7FB9);
t_mcu_register x_sgdma_start_fifo1   at_mcu(7FBA);  // rw
t_mcu_register x_sgdma_done_fifo1    at_mcu(7FBB);  // rw
t_mcu_register x_sgdma_adhi1         at_mcu(7FBC);
t_mcu_register x_sgdma_adlo1         at_mcu(7FBD);
t_mcu_register x_sgdma_szhi1         at_mcu(7FBE);
t_mcu_register x_sgdma_szlo1         at_mcu(7FBF);
t_mcu_register x_sgdma_total_pkts1   at_mcu(7FC0);
t_mcu_register x_sgdma_done_pkts1    at_mcu(7FC1);
t_mcu_register x_sgdma_sts1          at_mcu(7FC2);
t_mcu_register x_sgdma_cmd1          at_mcu(7FC3);
t_mcu_register x_sgdma_start_fifo2   at_mcu(7FC4);  // rw
t_mcu_register x_sgdma_done_fifo2    at_mcu(7FC5);  // rw
t_mcu_register x_sgdma_adhi2         at_mcu(7FC6);
t_mcu_register x_sgdma_adlo2         at_mcu(7FC7);
t_mcu_register x_sgdma_szhi2         at_mcu(7FC8);
t_mcu_register x_sgdma_szlo2         at_mcu(7FC9);
t_mcu_register x_sgdma_total_pkts2   at_mcu(7FCA);
t_mcu_register x_sgdma_done_pkts2    at_mcu(7FCB);
t_mcu_register x_sgdma_sts2          at_mcu(7FCC);
t_mcu_register x_sgdma_cmd2          at_mcu(7FCD);
t_mcu_register x_sgdma_start_fifo3   at_mcu(7FCE);  // rw
t_mcu_register x_sgdma_done_fifo3    at_mcu(7FCF);  // rw
t_mcu_register x_sgdma_adhi3         at_mcu(7FD0);
t_mcu_register x_sgdma_adlo3         at_mcu(7FD1);
t_mcu_register x_sgdma_szhi3         at_mcu(7FD2);
t_mcu_register x_sgdma_szlo3         at_mcu(7FD3);
t_mcu_register x_sgdma_total_pkts3   at_mcu(7FD4);
t_mcu_register x_sgdma_done_pkts3    at_mcu(7FD5);
t_mcu_register x_sgdma_sts3          at_mcu(7FD6);
t_mcu_register x_sgdma_cmd3          at_mcu(7FD7);
// x_sgdma_sts# bits
#define kbm_sgdma_busy               0x80
#define kbm_sgdma_isa_done           0x40
#define kbm_sgdma_m2m_incomplete     0x20
#define kbm_sgdma_done_fifo_full     0x08
#define kbm_sgdma_done_fifo_empty    0x04
#define kbm_sgdma_start_fifo_full    0x02
#define kbm_sgdma_start_fifo_empty   0x01
// x_sgdma_cmd# bits
#define kbm_sgdma_pkt_hdr            0x04
#define kbm_sgdma_no_pkt_hdr         0x00
#define kbm_sgdma_memop              0x02
#define kbm_sgdma_isaop              0x00
#define kbm_sgdma_enable             0x01
#define kbm_sgdma_disable            0x00

//------------------------------------------------------------------------------
t_mcu_register x_pio_adhi            at_mcu(7FD8);
t_mcu_register x_pio_admid           at_mcu(7FD9);
t_mcu_register x_pio_adlo            at_mcu(7FDA);
t_mcu_register x_pio_data            at_mcu(7FDB);
t_mcu_register x_pio_csr             at_mcu(7FDC);
// x_pio_csr bits
#define kbm_pio_busy                 0x80
#define kbm_pio_3clks                0x18
#define kbm_pio_4clks                0x20
#define kbm_pio_5clks                0x28
#define kbm_pio_6clks                0x30
#define kbm_pio_isamem               0x40
#define kbm_pio_isaio                0x00
#define kbm_pio_xfer_disable         0x00
#define kbm_pio_xfer_write           0x01
#define kbm_pio_xfer_read            0x02
#define kbm_pio_xfer_readmulti       0x03

#endif  // defined(k_mcu_97102) || defined(k_mcu_97FDC)
#endif  // k_10x_family

//------------------------------------------------------------------------------
//
//  2222    000   0    0
//      2  0   0   0  0
//   222   0   0    00    20X MCU FAMILY REGISTER DECLARATIONS
//  2      0   0   0  0
//  22222   000   0    0