📄 mcu.h
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#define kbm_txstat_a_ep3tx_full 0x40 // r
#define kbm_txstat_a_ep2tx_empty 0x20 // r
#define kbm_txstat_a_ep2tx_full 0x10 // r
#define kbm_txstat_a_ep1tx_empty 0x08 // r
#define kbm_txstat_a_ep1tx_full 0x04 // r
#define kbm_txstat_a_ep0tx_empty 0x02 // r
#define kbm_txstat_a_ep0tx_full 0x01 // r
//------------------------------------------------------------------------------
t_mcu_register x_txstat_b at_mcu(7F61); // r tx pkt fifo status reg (ep4-7)
// x_txstat_b bits
#define kbm_txstat_b_ep7tx_empty 0x80 // r
#define kbm_txstat_b_ep7tx_full 0x40 // r
#define kbm_txstat_b_ep6tx_empty 0x20 // r
#define kbm_txstat_b_ep6tx_full 0x10 // r
#define kbm_txstat_b_ep5tx_empty 0x08 // r
#define kbm_txstat_b_ep5tx_full 0x04 // r
#define kbm_txstat_b_ep4tx_empty 0x02 // r
#define kbm_txstat_b_ep4tx_full 0x01 // r
//------------------------------------------------------------------------------
t_mcu_register x_txstat_c at_mcu(7F62); // r tx pkt fifo status reg (ep8-11)
// x_txstat_c bits
#define kbm_txstat_c_ep11tx_empty 0x80 // r
#define kbm_txstat_c_ep11tx_full 0x40 // r
#define kbm_txstat_c_ep10tx_empty 0x20 // r
#define kbm_txstat_c_ep10tx_full 0x10 // r
#define kbm_txstat_c_ep9tx_empty 0x08 // r
#define kbm_txstat_c_ep9tx_full 0x04 // r
#define kbm_txstat_c_ep8tx_empty 0x02 // r
#define kbm_txstat_c_ep8tx_full 0x01 // r
//------------------------------------------------------------------------------
t_mcu_register x_txstat_d at_mcu(7F63); // r tx pkt fifo status reg (ep12-15)
// x_txstat_d bits
#define kbm_txstat_d_ep15tx_empty 0x80 // r
#define kbm_txstat_d_ep15tx_full 0x40 // r
#define kbm_txstat_d_ep14tx_empty 0x20 // r
#define kbm_txstat_d_ep14tx_full 0x10 // r
#define kbm_txstat_d_ep13tx_empty 0x08 // r
#define kbm_txstat_d_ep13tx_full 0x04 // r
#define kbm_txstat_d_ep12tx_empty 0x02 // r
#define kbm_txstat_d_ep12tx_full 0x01 // r
//------------------------------------------------------------------------------
// these are txfifo related symbols that facilitate implementation of the hal
//------------------------------------------------------------------------------
// txfifo addresses
#define k_txf_addr0 k_addr_txstata
#define k_txf_addr1 k_addr_txstata
#define k_txf_addr2 k_addr_txstata
#define k_txf_addr3 k_addr_txstata
#define k_txf_addr4 k_addr_txstatb
#define k_txf_addr5 k_addr_txstatb
#define k_txf_addr6 k_addr_txstatb
#define k_txf_addr7 k_addr_txstatb
#define k_txf_addr9 k_addr_txstatc
#define k_txf_addr9 k_addr_txstatc
#define k_txf_addr10 k_addr_txstatc
#define k_txf_addr11 k_addr_txstatc
#define k_txf_addr12 k_addr_txstatd
#define k_txf_addr13 k_addr_txstatd
#define k_txf_addr14 k_addr_txstatd
#define k_txf_addr15 k_addr_txstatd
// txfifo compare masks
#define kbm_txf_mask0 0x03
#define kbm_txf_mask1 0x0C
#define kbm_txf_mask2 0x30
#define kbm_txf_mask3 0xC0
#define kbm_txf_mask4 0x03
#define kbm_txf_mask5 0x0C
#define kbm_txf_mask6 0x30
#define kbm_txf_mask7 0xC0
#define kbm_txf_mask8 0x03
#define kbm_txf_mask9 0x0C
#define kbm_txf_mask10 0x30
#define kbm_txf_mask11 0xC0
#define kbm_txf_mask12 0x03
#define kbm_txf_mask13 0x0C
#define kbm_txf_mask14 0x30
#define kbm_txf_mask15 0xC0
// txfifo compare empty values
#define kbm_txf_cmpr_epty0 0x02
#define kbm_txf_cmpr_epty1 0x08
#define kbm_txf_cmpr_epty2 0x20
#define kbm_txf_cmpr_epty3 0x80
#define kbm_txf_cmpr_epty4 0x02
#define kbm_txf_cmpr_epty5 0x08
#define kbm_txf_cmpr_epty6 0x20
#define kbm_txf_cmpr_epty7 0x80
#define kbm_txf_cmpr_epty8 0x02
#define kbm_txf_cmpr_epty9 0x08
#define kbm_txf_cmpr_epty10 0x20
#define kbm_txf_cmpr_epty11 0x80
#define kbm_txf_cmpr_epty12 0x02
#define kbm_txf_cmpr_epty13 0x08
#define kbm_txf_cmpr_epty14 0x20
#define kbm_txf_cmpr_epty15 0x80
// txfifo compare full values
#define kbm_txf_cmpr_full0 0x01
#define kbm_txf_cmpr_full1 0x04
#define kbm_txf_cmpr_full2 0x10
#define kbm_txf_cmpr_full3 0x40
#define kbm_txf_cmpr_full4 0x01
#define kbm_txf_cmpr_full5 0x04
#define kbm_txf_cmpr_full6 0x10
#define kbm_txf_cmpr_full7 0x40
#define kbm_txf_cmpr_full8 0x01
#define kbm_txf_cmpr_full9 0x04
#define kbm_txf_cmpr_full10 0x10
#define kbm_txf_cmpr_full11 0x40
#define kbm_txf_cmpr_full12 0x01
#define kbm_txf_cmpr_full13 0x04
#define kbm_txf_cmpr_full14 0x10
#define kbm_txf_cmpr_full15 0x40
// address of the txstat registers
#define k_addr_txstata 0x7F60 // r tx pkt fifo status reg (ep0-3)
#define k_addr_txstatb 0x7F61 // r tx pkt fifo status reg (ep4-7)
#define k_addr_txstatc 0x7F62 // r tx pkt fifo status reg (ep8-11)
#define k_addr_txstatd 0x7F63 // r tx pkt fifo status reg (ep12-15)
//------------------------------------------------------------------------------
t_mcu_register x_tx_mgmt1 at_mcu(7F67); // rw controls auto/manual deallocate
// x_tx_mgmt1 bits
#define kbm_tx_mgmt_mem_dall 0x01 // rw
//------------------------------------------------------------------------------
#define x_ep_ctrl 0x7F80 // base accress to treat ep_ctrl regs as an array
t_mcu_register x_ep_ctrl0 at_mcu(7F80); // rw endpoint 0 control register
t_mcu_register x_ep_ctrl1 at_mcu(7F81); // rw endpoint 1 control register
t_mcu_register x_ep_ctrl2 at_mcu(7F82); // rw endpoint 2 control register
t_mcu_register x_ep_ctrl3 at_mcu(7F83); // rw endpoint 3 control register
t_mcu_register x_ep_ctrl4 at_mcu(7F84); // rw endpoint 4 control register
t_mcu_register x_ep_ctrl5 at_mcu(7F85); // rw endpoint 5 control register
t_mcu_register x_ep_ctrl6 at_mcu(7F86); // rw endpoint 6 control register
t_mcu_register x_ep_ctrl7 at_mcu(7F87); // rw endpoint 7 control register
t_mcu_register x_ep_ctrl8 at_mcu(7F88); // rw endpoint 8 control register
t_mcu_register x_ep_ctrl9 at_mcu(7F89); // rw endpoint 9 control register
t_mcu_register x_ep_ctrl10 at_mcu(7F8A); // rw endpoint 10 control register
t_mcu_register x_ep_ctrl11 at_mcu(7F8B); // rw endpoint 11 control register
t_mcu_register x_ep_ctrl12 at_mcu(7F8C); // rw endpoint 12 control register
t_mcu_register x_ep_ctrl13 at_mcu(7F8D); // rw endpoint 13 control register
t_mcu_register x_ep_ctrl14 at_mcu(7F8E); // rw endpoint 14 control register
t_mcu_register x_ep_ctrl15 at_mcu(7F8F); // rw endpoint 15 control register
// x_ep_ctrl0..15 bits
#define kbm_epctrl_tx_iso 0x80 // rw
#define kbm_epctrl_rx_iso 0x40 // rw
#define kbm_epctrl_tx_cont1 0x20 // rw
#define kbm_epctrl_rx_cont1 0x10 // rw
#define kbm_epctrl_tx_cont0 0x08 // rw
#define kbm_epctrl_rx_cont0 0x04 // rw
#define kbm_epctrl_tx_toggle 0x02 // rw
#define kbm_epctrl_rx_toggle 0x01 // r
// tc_cont[1:0); bit field
#define kbm_epctrl_tx_cont_msk 0x28 // rw
#define kbm_epctrl_tx_busy 0x28 // rw
#define kbm_epctrl_tx_enable 0x20 // rw
#define kbm_epctrl_tx_stall 0x08 // rw
#define kbm_epctrl_tx_disable 0x00 // rw
// rx_cont[1:0); bit field
#define kbm_epctrl_rx_cont_msk 0x14 // rw
#define kbm_epctrl_rx_busy 0x14 // rw
#define kbm_epctrl_rx_enable 0x10 // rw
#define kbm_epctrl_rx_stall 0x04 // rw
#define kbm_epctrl_rx_disable 0x00 // rw
//------------------------------------------------------------------------------
t_mcu_register x_framel at_mcu(7F90); // r usb frame count low
t_mcu_register x_frameh at_mcu(7F91); // r usb frame count high
//------------------------------------------------------------------------------
t_mcu_register x_sie_addr at_mcu(7F92); // rw usb local address register
// x_sie_addr bits
#define kbm_sie_addr_rx_all 0x80 // rw
//------------------------------------------------------------------------------
t_mcu_register x_sie_stat at_mcu(7F93); // r sie status register
// x_sie_stat_bits
#define kbm_sie_stat_err 0x80 // r
#define kbm_sie_stat_timeout 0x40 // r
#define kbm_sie_stat_setup_token 0x20 // r
#define kbm_sie_stat_sof_token 0x10 // r
#define kbm_sie_stat_pre_token 0x08 // r
#define kbm_sie_stat_ack 0x04 // r
#define kbm_sie_stat_usb_reset 0x02 // r
#define kbm_sie_stat_eot 0x01 // r
//------------------------------------------------------------------------------
t_mcu_register x_sie_ctrl at_mcu(7F94); // rw sie control register
// x_sie_ctrl_bits
#define kbm_sie_ctrl_siedma_disable 0x80 // rw
#define kbm_sie_ctrl_force_rxok 0x40 // rw
#define kbm_sie_ctrl_force_ttag 0x20 // rw
#define kbm_sie_ctrl_force_rxovflo 0x10 // rw
#define kbm_sie_ctrl_force_txabort 0x08 // rw
#define kbm_sie_ctrl_force_eot 0x04 // rw
#define kbm_sie_ctrl_rtag_in 0x02 // r
#define kbm_sie_ctrl_txok_in 0x01 // r
//------------------------------------------------------------------------------
#ifndef k_mcu_97100 // this register is not present on the '100
t_mcu_register x_sie_ctrl2 at_mcu(7FA9); // rw sie control register 2
// x_sie_ctrl2 bits
#define kbm_self_powered 0x80 // 102 rev B (reserved in 102 rev A and FDC)
#define kbm_global_resume 0x10 // 102 rev B (reserved in 102 rev A and FDC)
#define kbm_global_suspend 0x08 // 102 rev B (reserved in 102 rev A and FDC)
#define kbm_set_busy_on_setup 0x04
#define kbm_iso_limit1023 0x00
#define kbm_iso_limit512 0x01
#define kbm_iso_limit256 0x02
#define kbm_iso_limit0xff 0x03
#endif
//------------------------------------------------------------------------------
t_mcu_register x_sie_config at_mcu(7F98); // rw sie configuration register
// x_sie_config bits
#define kbm_sie_config_usb_reset 0x01 // r
#define kbm_sie_config_usb_resume 0x02 // r
#define kbm_sie_config_sie_resume 0x04 // rw
#define kbm_sie_config_sie_suspend 0x08 // rw
#define kbm_sie_config_extframe_enable 0x10 // rw
#define kbm_sie_config_rst_frame 0x20 // rw
#define kbm_sie_config_rst_sie 0x40 // rw
#define kbm_sie_config_fs_enable 0x80 // rw
//------------------------------------------------------------------------------
t_mcu_register x_alt_addr1 at_mcu(7F99); // rw 1st alternate address reg
t_mcu_register x_sie_tst3 at_mcu(7F9A); // reserved for test
t_mcu_register x_sie_tst4 at_mcu(7F9B); // reserved for test
t_mcu_register x_sie_tst5 at_mcu(7F9C); // reserved for test
t_mcu_register x_sie_tst6 at_mcu(7F9D); // reserved for test
t_mcu_register x_alt_addr2 at_mcu(7F9E); // rw 2nd alternate address reg
t_mcu_register x_alt_addr3 at_mcu(7F9F); // rw 3rd alternate address reg
// x_alt_addr1..3 bits
#define kbm_alt_addr_enable 0x80 // rw
#define kmb_alt_addr_msk 0x7f // rw
//------------------------------------------------------------------------------
// flags_endp bits
// note: "oversized packet" error drops packet and asserts rx_ovrn irq
#define kbm_pkt_hdr_bad_crc 0x80
#define kbm_pkt_hdr_last_tog 0x40
#define kbm_pkt_hdr_same_tog 0x20
//------------------------------------------------------------------------------
// dmac registers in isa space
#define k_dma_iobase 0x00 // dma base register
#define k_dma_baseaddr 0x0000
//------------------------------------------------------------------------------
// these are deprecated, use the code in dmac.h and dmac.c for better performance
t_isa_register i_dma_addr0 at_isa(0x0000); // rw channel 0 current address
t_isa_register i_dma_cnt0 at_isa(0x0001); // rw channel 0 byte count
t_isa_register i_dma_addr1 at_isa(0x0002); // rw channel 1 current address
t_isa_register i_dma_cnt1 at_isa(0x0003); // rw channel 1 byte count
t_isa_register i_dma_addr2 at_isa(0x0004); // rw channel 2 current address
t_isa_register i_dma_cnt2 at_isa(0x0005); // rw channel 2 byte count
t_isa_register i_dma_addr3 at_isa(0x0006); // rw channel 3 current address
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