cpu.h

U盘控制器USB97C223的固件代码,对2kPAGE NAND FLASH 有很好的支持.

/*============================================================================
  ____________________________________________________________________________
                                ______________________________________________
   SSSS  M   M          CCCC          Standard Microsystems Corporation
  S      MM MM   SSSS  C                    Austin Design Center
   SSS   M M M  S      C                 11000 N. Mopac Expressway
      S  M   M   SSS   C                Stonelake Bldg. 6, Suite 500
  SSSS   M   M      S   CCCC                Austin, Texas 78759
                SSSS            ______________________________________________
  ____________________________________________________________________________

  Copyright(C) 1999, Standard Microsystems Corporation
  All Rights Reserved.

  This program code listing is proprietary to SMSC and may not be copied,
  distributed, or used without a license to do so.  Such license may have
  Limited or Restricted Rights. Please refer to the license for further
  clarification.
  ____________________________________________________________________________

  Notice: The program contained in this listing is a proprietary trade
  secret of SMSC, Hauppauge, New York, and is copyrighted
  under the United States Copyright Act of 1976 as an unpublished work,
  pursuant to Section 104 and Section 408 of Title XVII of the United
  States code. Unauthorized copying, adaption, distribution, use, or
  display is prohibited by this law.
  ____________________________________________________________________________

  Use, duplication, or disclosure by the Government is subject to
  restrictions as set forth in subparagraph(c)(1)(ii) of the Rights
  in Technical Data and Computer Software clause at DFARS 52.227-7013.
  Contractor/Manufacturer is Standard Microsystems Corporation,
  80 Arkay Drive, Hauppauge, New York, 1178-8847.
  ____________________________________________________________________________
  ____________________________________________________________________________

  cpu.h - cpu register definitions.
  ____________________________________________________________________________

  comments tbd
  ____________________________________________________________________________

  Revision History
  Date      Who  Comment
  ________  ___  _____________________________________________________________
  07/16/99  tbh  initial version
  03/17/01  tbh  merged in the dw8051 extensions.
  07/03/03  ds   Added the flip 8051 (Dolphin) extensions
============================================================================*/

//DS: Note to developer: The definitions in the old code has been retained for now. But the new definitions
//have been coded according to the new SMSC Code standards. So, there there are no upper case definitions.
//Thus the old ones will also, have to be changed to the new standards. 

//------------------------------------------------------------------------------
// cpu registers
#define _define_cpu_register(__name, __addr) sfr __name = 0x##__addr
#define _cpu_register_rd(__ref) (__ref)
#define _cpu_register_wr(__ref, __datum) (__ref)=(__datum)
#define _cpu_register_setbit(__ref, __bitix) _cpu_register_wr((__ref), _cpu_register_rd((__ref)) |(1 << __bitix))
#define _cpu_register_clrbit(__ref, __bitix) _cpu_register_wr((__ref), _cpu_register_rd((__ref)) & ~(1 << __bitix))
#define _cpu_register_set_bits(__ref, __bitmsk) _cpu_register_wr((__ref), _cpu_register_rd((__ref)) |(__bitmsk))
#define _cpu_register_clr_bits(__ref, __bitmsk) _cpu_register_wr((__ref), _cpu_register_rd((__ref)) & ~(__bitmsk))

//------------------------------------------------------------------------------
//
//   888    000   555550    1
//  8   8  0   0  5        11
//   888   0   0  55555     1    CPU REGISTERS
//  8   8  0   0       5    1
//   888    000   55555   11111
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Standard 8051 special function registers
//------------------------------------------------------------------------------
sfr P0 = 0x80;    // Port0
sfr P1 = 0x90;    // Port1
sfr P2 = 0xA0;    // Port2
sfr P3 = 0xB0;    // Port3
sfr PSW = 0xD0;   // Program Status Word
sfr ACC = 0xE0;   // Accumulator
sfr B = 0xF0;     // B Register
sfr SP = 0x81;    // Stack Pointer
sfr DPL = 0x82;   // Data Pointer Low byte (part of DPTR)
sfr DPH = 0x83;   // Data Pointer High byte (part of DPTR)
sfr PCON = 0x87;  // Power Control
sfr TCON = 0x88;  // Timer Control
sfr TMOD = 0x89;  // Timer Mode
sfr TL0 = 0x8A;   // Timer Low 0
sfr TL1 = 0x8B;   // Timer Low 1
sfr TH0 = 0x8C;   // Timer High 0
sfr TH1 = 0x8D;   // Timer High 1
sfr IE = 0xA8;    // Interrupt Enable
sfr IP = 0xB8;    // Interrupt Priority
sfr SCON = 0x98;  // Serial Control
sfr SBUF = 0x99;  // Serial data Buffer
//------------------------------------------------------------------------------
// PSW -- Program Status Word (bit 1 reserved)
//------------------------------------------------------------------------------
sbit CY = 0xD7;   // CarrY flag
sbit AC = 0xD6;   // Auxiliary Carry flag
sbit F0 = 0xD5;   // Flag 0
sbit RS1 = 0xD4;  // Register bank Select, high bit 1
sbit RS0 = 0xD3;  // Register bank Select, low bit 0
sbit OV = 0xD2;   // OVerflow flag
sbit P = 0xD0;    // Parity flag
//------------------------------------------------------------------------------
// TCON -- Timer Control
//------------------------------------------------------------------------------
sbit TF1 = 0x8F;  // Timer overflow Flag 1
sbit TR1 = 0x8E;  // Timer Run 1
sbit TF0 = 0x8D;  // Timer overflow Flag 0
sbit TR0 = 0x8C;  // Timer Run 0
sbit IE1 = 0x8B;  // Interrupt Edge 1
sbit IT1 = 0x8A;  // Interrupt Type 1
sbit IE0 = 0x89;  // Interrupt Edge 0
sbit IT0 = 0x88;  // Interrupt Type 0
//------------------------------------------------------------------------------
// IE -- Interrupt Enable (bits 5-6 reserved)
//------------------------------------------------------------------------------
sbit EA = 0xAF;   // Enable All irq's, gated
sbit ES = 0xAC;   // Enable Serial port irq
sbit ET1 = 0xAB;  // Enable Timer1 overflow irq
sbit EX1 = 0xAA;  // Enable External irq1
sbit ET0 = 0xA9;  // Enable Timer0 overflow irq
sbit EX0 = 0xA8;  // Enable External irq0
//------------------------------------------------------------------------------
// IP -- Interrupt Priority (bits 5-7 reserved)
//------------------------------------------------------------------------------
sbit PS = 0xBC;   // Priority Serial port irq
sbit PT1 = 0xBB;  // Priority Timer1 irq
sbit PX1 = 0xBA;  // Priority eXternal irq1
sbit PT0 = 0xB9;  // Priority Timer0 irq
sbit PX0 = 0xB8;  // Priority eXternal irq0
//------------------------------------------------------------------------------
// P3 -- Port3
//------------------------------------------------------------------------------
sbit RD = 0xB7;
sbit WR = 0xB6;
sbit T1 = 0xB5;
sbit T0 = 0xB4;
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD = 0xB1;
sbit RXD = 0xB0;
//------------------------------------------------------------------------------
// SCON -- Serial port CONtrol
//------------------------------------------------------------------------------
sbit SM0 = 0x9F;  // Serial port Mode, bit 0
sbit SM1 = 0x9E;  // Serial port Mode, bit 1
sbit SM2 = 0x9D;  // Serial port Mode, bit 2
sbit REN = 0x9C;  // Reception ENable
sbit TB8 = 0x9B;  // Transmit Bit 8
sbit RB8 = 0x9A;  // Receive Bit 8
sbit TI = 0x99;   // Transmit Irq flag
sbit RI = 0x98;   // Receive Irq flag

#ifdef  k_cpu_dw8051
//-------------------------------------------------------------------------v-v-v

//------------------------------------------------------------------------------
//
//  DDDD   W   W   888    000   555550    1
//  D   D  W   W  8   8  0   0  5        11
//  D   D  W W W   888   0   0  55555     1    CPU MACROCELL EXTENSIONS
//  D   D  WW WW  8   8  0   0       5    1
//  DDDD   W   W   888    000   55555   11111
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// DesignWare DW8051 Macrocell extensions to standard 8051 registers
//------------------------------------------------------------------------------
sfr DPL1   = 0x84;
sfr DPH1   = 0x85;
sfr DPS    = 0x86;
sfr CKCON  = 0x8E;
sfr SPCFNC = 0x8F;
sfr EXIF   = 0x91;
sfr MPAGE  = 0x92;
sfr SCON0  = 0x98;
sfr SBUF0  = 0x99;
sfr SCON1  = 0xC0;  // not implemented
sfr SBUF1  = 0xC1;  // not implemented
sfr T2CON  = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2    = 0xCC;
sfr TH2    = 0xCD;
sfr EICON  = 0xD8;
sfr EIE    = 0xE8;
sfr EIP    = 0xF8;
//------------------------------------------------------------------------------
// DPS-- data pointer select
//------------------------------------------------------------------------------
#define kbm_SEL 0x01
//------------------------------------------------------------------------------
// CKCON --
//------------------------------------------------------------------------------
#define kbm_T2M 0x20
#define kbm_T1M 0x10
#define kbm_T0M 0x08
#define kbm_MD2 0x04
#define kbm_MD1 0x02
#define kbm_MD0 0x01
//------------------------------------------------------------------------------
// EXIF --
//------------------------------------------------------------------------------
#define kbm_IE5 0x80
#define kbm_IE4 0x40
#define kbm_IE3 0x20
#define kbm_IE2 0x10
//------------------------------------------------------------------------------
// SPCFNC --
//------------------------------------------------------------------------------
#define kbm_WRS 0x01
//------------------------------------------------------------------------------
// IE -- extras
//------------------------------------------------------------------------------
sbit ES1   = 0xAE;  // Enable serial port 1 irq
sbit ET2   = 0xAD;  // Enable Timer2 overflow irq
sbit ES0   = 0xAC;  // Enable serial port 0 irq (same as ES)
//------------------------------------------------------------------------------
// IP -- extras
//------------------------------------------------------------------------------
sbit PS1 = 0xBE;  // priority serial port 1 interrupt (not implemented)
sbit PT2 = 0xBD;  // priotiry timer2 irq
sbit PS0 = 0xBC;  // Priority Serial port irq  (same as PS)
//------------------------------------------------------------------------------
// SCON0 -- redefinitions
//------------------------------------------------------------------------------
sbit SM00 = 0x9F;
sbit SM10 = 0x9E;
sbit SM20 = 0x9D;
sbit REN0 = 0x9C;
sbit TB80 = 0x9B;
sbit RB80 = 0x9A;
sbit TI0  = 0x99;
sbit RI0  = 0x98;
//------------------------------------------------------------------------------
// SCON1 -- extras, but not implemented
//------------------------------------------------------------------------------
sbit SM01 = 0xC7;
sbit SM11 = 0xC6;
sbit SM21 = 0xC5;
sbit REN1 = 0xC4;
sbit TB81 = 0xC3;