📄 regs-gpio.h
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#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)#define S3C2410_GPF3_INP (0x00 << 6)#define S3C2410_GPF3_OUTP (0x01 << 6)#define S3C2410_GPF3_EINT3 (0x02 << 6)#define S3C2400_GPF3_TXD1 (0x02 << 6)#define S3C2400_GPF3_IICSCL (0x03 << 6)#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)#define S3C2410_GPF4_INP (0x00 << 8)#define S3C2410_GPF4_OUTP (0x01 << 8)#define S3C2410_GPF4_EINT4 (0x02 << 8)#define S3C2400_GPF4_nRTS0 (0x02 << 8)#define S3C2400_GPF4_nXBACK (0x03 << 8)#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)#define S3C2410_GPF5_INP (0x00 << 10)#define S3C2410_GPF5_OUTP (0x01 << 10)#define S3C2410_GPF5_EINT5 (0x02 << 10)#define S3C2400_GPF5_nCTS0 (0x02 << 10)#define S3C2400_GPF5_nXBREQ (0x03 << 10)#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)#define S3C2410_GPF6_INP (0x00 << 12)#define S3C2410_GPF6_OUTP (0x01 << 12)#define S3C2410_GPF6_EINT6 (0x02 << 12)#define S3C2400_GPF6_CLKOUT (0x02 << 12)#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)#define S3C2410_GPF7_INP (0x00 << 14)#define S3C2410_GPF7_OUTP (0x01 << 14)#define S3C2410_GPF7_EINT7 (0x02 << 14)#define S3C2410_GPF_PUPDIS(x) (1<<(x))/* S3C2410: * Port G consists of 8 GPIO/IRQ/Special function * * GPGCON has 2 bits for each of the input pins on port F * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func * * pull up works like all other ports. * * S3C2400: * Port G consists of 10 GPIO/Special function*/#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)#define S3C2410_GPG0_INP (0x00 << 0)#define S3C2410_GPG0_OUTP (0x01 << 0)#define S3C2410_GPG0_EINT8 (0x02 << 0)#define S3C2400_GPG0_I2SLRCK (0x02 << 0)#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)#define S3C2410_GPG1_INP (0x00 << 2)#define S3C2410_GPG1_OUTP (0x01 << 2)#define S3C2410_GPG1_EINT9 (0x02 << 2)#define S3C2400_GPG1_I2SSCLK (0x02 << 2)#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)#define S3C2410_GPG2_INP (0x00 << 4)#define S3C2410_GPG2_OUTP (0x01 << 4)#define S3C2410_GPG2_EINT10 (0x02 << 4)#define S3C2400_GPG2_CDCLK (0x02 << 4)#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)#define S3C2410_GPG3_INP (0x00 << 6)#define S3C2410_GPG3_OUTP (0x01 << 6)#define S3C2410_GPG3_EINT11 (0x02 << 6)#define S3C2400_GPG3_I2SSDO (0x02 << 6)#define S3C2400_GPG3_I2SSDI (0x03 << 6)#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)#define S3C2410_GPG4_INP (0x00 << 8)#define S3C2410_GPG4_OUTP (0x01 << 8)#define S3C2410_GPG4_EINT12 (0x02 << 8)#define S3C2400_GPG4_MMCCLK (0x02 << 8)#define S3C2400_GPG4_I2SSDI (0x03 << 8)#define S3C2410_GPG4_LCDPWREN (0x03 << 8)#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)#define S3C2410_GPG5_INP (0x00 << 10)#define S3C2410_GPG5_OUTP (0x01 << 10)#define S3C2410_GPG5_EINT13 (0x02 << 10)#define S3C2400_GPG5_MMCCMD (0x02 << 10)#define S3C2400_GPG5_IICSDA (0x03 << 10)#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)#define S3C2410_GPG6_INP (0x00 << 12)#define S3C2410_GPG6_OUTP (0x01 << 12)#define S3C2410_GPG6_EINT14 (0x02 << 12)#define S3C2400_GPG6_MMCDAT (0x02 << 12)#define S3C2400_GPG6_IICSCL (0x03 << 12)#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)#define S3C2410_GPG7_INP (0x00 << 14)#define S3C2410_GPG7_OUTP (0x01 << 14)#define S3C2410_GPG7_EINT15 (0x02 << 14)#define S3C2410_GPG7_SPICLK1 (0x03 << 14)#define S3C2400_GPG7_SPIMISO (0x02 << 14)#define S3C2400_GPG7_IICSDA (0x03 << 14)#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)#define S3C2410_GPG8_INP (0x00 << 16)#define S3C2410_GPG8_OUTP (0x01 << 16)#define S3C2410_GPG8_EINT16 (0x02 << 16)#define S3C2400_GPG8_SPIMOSI (0x02 << 16)#define S3C2400_GPG8_IICSCL (0x03 << 16)#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)#define S3C2410_GPG9_INP (0x00 << 18)#define S3C2410_GPG9_OUTP (0x01 << 18)#define S3C2410_GPG9_EINT17 (0x02 << 18)#define S3C2400_GPG9_SPICLK (0x02 << 18)#define S3C2400_GPG9_MMCCLK (0x03 << 18)#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)#define S3C2410_GPG10_INP (0x00 << 20)#define S3C2410_GPG10_OUTP (0x01 << 20)#define S3C2410_GPG10_EINT18 (0x02 << 20)#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)#define S3C2410_GPG11_INP (0x00 << 22)#define S3C2410_GPG11_OUTP (0x01 << 22)#define S3C2410_GPG11_EINT19 (0x02 << 22)#define S3C2410_GPG11_TCLK1 (0x03 << 22)#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)#define S3C2410_GPG12_INP (0x00 << 24)#define S3C2410_GPG12_OUTP (0x01 << 24)#define S3C2410_GPG12_EINT20 (0x02 << 24)#define S3C2410_GPG12_XMON (0x03 << 24)#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)#define S3C2410_GPG13_INP (0x00 << 26)#define S3C2410_GPG13_OUTP (0x01 << 26)#define S3C2410_GPG13_EINT21 (0x02 << 26)#define S3C2410_GPG13_nXPON (0x03 << 26)#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)#define S3C2410_GPG14_INP (0x00 << 28)#define S3C2410_GPG14_OUTP (0x01 << 28)#define S3C2410_GPG14_EINT22 (0x02 << 28)#define S3C2410_GPG14_YMON (0x03 << 28)#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)#define S3C2410_GPG15_INP (0x00 << 30)#define S3C2410_GPG15_OUTP (0x01 << 30)#define S3C2410_GPG15_EINT23 (0x02 << 30)#define S3C2410_GPG15_nYPON (0x03 << 30)#define S3C2410_GPG_PUPDIS(x) (1<<(x))/* Port H consists of11 GPIO/serial/Misc pins * * GPGCON has 2 bits for each of the input pins on port F * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func * * pull up works like all other ports.*/#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)#define S3C2410_GPH0_INP (0x00 << 0)#define S3C2410_GPH0_OUTP (0x01 << 0)#define S3C2410_GPH0_nCTS0 (0x02 << 0)#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)#define S3C2410_GPH1_INP (0x00 << 2)#define S3C2410_GPH1_OUTP (0x01 << 2)#define S3C2410_GPH1_nRTS0 (0x02 << 2)#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)#define S3C2410_GPH2_INP (0x00 << 4)#define S3C2410_GPH2_OUTP (0x01 << 4)#define S3C2410_GPH2_TXD0 (0x02 << 4)#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)#define S3C2410_GPH3_INP (0x00 << 6)#define S3C2410_GPH3_OUTP (0x01 << 6)#define S3C2410_GPH3_RXD0 (0x02 << 6)#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)#define S3C2410_GPH4_INP (0x00 << 8)#define S3C2410_GPH4_OUTP (0x01 << 8)#define S3C2410_GPH4_TXD1 (0x02 << 8)#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)#define S3C2410_GPH5_INP (0x00 << 10)#define S3C2410_GPH5_OUTP (0x01 << 10)#define S3C2410_GPH5_RXD1 (0x02 << 10)#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)#define S3C2410_GPH6_INP (0x00 << 12)#define S3C2410_GPH6_OUTP (0x01 << 12)#define S3C2410_GPH6_TXD2 (0x02 << 12)#define S3C2410_GPH6_nRTS1 (0x03 << 12)#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)#define S3C2410_GPH7_INP (0x00 << 14)#define S3C2410_GPH7_OUTP (0x01 << 14)#define S3C2410_GPH7_RXD2 (0x02 << 14)#define S3C2410_GPH7_nCTS1 (0x03 << 14)#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)#define S3C2410_GPH8_INP (0x00 << 16)#define S3C2410_GPH8_OUTP (0x01 << 16)#define S3C2410_GPH8_UCLK (0x02 << 16)#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)#define S3C2410_GPH9_INP (0x00 << 18)#define S3C2410_GPH9_OUTP (0x01 << 18)#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)#define S3C2410_GPH10_INP (0x00 << 20)#define S3C2410_GPH10_OUTP (0x01 << 20)#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)/* miscellaneous control */#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)/* see clock.h for dclk definitions *//* pullup control on databus */#define S3C2410_MISCCR_SPUCR_HEN (0<<0)#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)#define S3C2410_MISCCR_SPUCR_LEN (0<<1)#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)#define S3C2400_MISCCR_SPUCR_LEN (0<<0)#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)#define S3C2400_MISCCR_SPUCR_HEN (0<<1)#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)#define S3C2400_MISCCR_HZ_STOPEN (0<<2)#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)#define S3C2410_MISCCR_USBDEV (0<<3)#define S3C2410_MISCCR_USBHOST (1<<3)#define S3C2410_MISCCR_CLK0_MPLL (0<<4)#define S3C2410_MISCCR_CLK0_UPLL (1<<4)#define S3C2410_MISCCR_CLK0_FCLK (2<<4)#define S3C2410_MISCCR_CLK0_HCLK (3<<4)#define S3C2410_MISCCR_CLK0_PCLK (4<<4)#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)#define S3C2410_MISCCR_CLK1_MPLL (0<<8)#define S3C2410_MISCCR_CLK1_UPLL (1<<8)#define S3C2410_MISCCR_CLK1_FCLK (2<<8)#define S3C2410_MISCCR_CLK1_HCLK (3<<8)#define S3C2410_MISCCR_CLK1_PCLK (4<<8)#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)#define S3C2410_MISCCR_USBSUSPND0 (1<<12)#define S3C2410_MISCCR_USBSUSPND1 (1<<13)#define S3C2410_MISCCR_nRSTCON (1<<16)#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)#define S3C2410_MISCCR_nEN_SCLKE (1<<19)#define S3C2410_MISCCR_SDSLEEP (7<<17)/* external interrupt control... *//* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 * * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 * * Samsung datasheet p9-25*/#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)/* values for S3C2410_EXTINT0/1/2 */#define S3C2410_EXTINT_LOWLEV (0x00)#define S3C2410_EXTINT_HILEV (0x01)#define S3C2410_EXTINT_FALLEDGE (0x02)#define S3C2410_EXTINT_RISEEDGE (0x04)#define S3C2410_EXTINT_BOTHEDGE (0x06)/* interrupt filtering conrrol for EINT16..EINT23 */#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)/* values for interrupt filtering */#define S3C2410_EINTFLT_PCLK (0x00)#define S3C2410_EINTFLT_EXTCLK (1<<7)#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)/* removed EINTxxxx defs from here, not meant for this *//* GSTATUS have miscellaneous information in them * */#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)#define S3C2410_GSTATUS0_nWAIT (1<<3)#define S3C2410_GSTATUS0_NCON (1<<2)#define S3C2410_GSTATUS0_RnB (1<<1)#define S3C2410_GSTATUS0_nBATTFLT (1<<0)#define S3C2410_GSTATUS1_IDMASK (0xffff0000)#define S3C2410_GSTATUS1_2410 (0x32410000)#define S3C2410_GSTATUS1_2440 (0x32440000)#define S3C2410_GSTATUS2_WTRESET (1<<2)#define S3C2410_GSTATUS2_OFFRESET (1<<1)#define S3C2410_GSTATUS2_PONRESET (1<<0)/* open drain control register */#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)#define S3C2400_OPENCR_OPC_CMDEN (1<<2)#define S3C2400_OPENCR_OPC_DATDIS (0<<3)#define S3C2400_OPENCR_OPC_DATEN (1<<3)#define S3C2400_OPENCR_OPC_MISODIS (0<<4)#define S3C2400_OPENCR_OPC_MISOEN (1<<4)#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)#endif /* __ASM_ARCH_REGS_GPIO_H */⌨️ 快捷键说明
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