📄 regs-gpio.h
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/* linux/include/asm/hardware/s3c2410/regs-gpio.h * * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> * http://www.simtec.co.uk/products/SWLINUX/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * S3C2410 GPIO register definitions * * Changelog: * 19-06-2003 BJD Created file * 23-06-2003 BJD Updated GSTATUS registers * 12-03-2004 BJD Updated include protection * 20-07-2004 BJD Added GPIO pin numbers, added Port A definitions * 04-10-2004 BJD Fixed number of bugs, added EXT IRQ filter defs * 17-10-2004 BJD Added GSTATUS1 register definitions * 18-11-2004 BJD Fixed definitions of GPE3, GPE4, GPE5 and GPE6 * 18-11-2004 BJD Added S3C2440 AC97 controls * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA * 28-Mar-2005 LCVR Fixed definition of GPB10 * 26-Oct-2005 BJD Added generic configuration types * 27-Nov-2005 LCVR Added definitions to S3C2400 registers * 15-Jan-2006 LCVR Written S3C24XX_GPIO_BASE() macro*/#ifndef __ASM_ARCH_REGS_GPIO_H#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))#define S3C2410_GPIO_BANKA (32*0)#define S3C2410_GPIO_BANKB (32*1)#define S3C2410_GPIO_BANKC (32*2)#define S3C2410_GPIO_BANKD (32*3)#define S3C2410_GPIO_BANKE (32*4)#define S3C2410_GPIO_BANKF (32*5)#define S3C2410_GPIO_BANKG (32*6)#define S3C2410_GPIO_BANKH (32*7)#ifdef CONFIG_CPU_S3C2400#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)#define S3C24XX_MISCCR S3C2400_MISCCR#else#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)#define S3C24XX_MISCCR S3C2410_MISCCR#endif /* CONFIG_CPU_S3C2400 *//* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ (2 * (S3C2400_BANKNUM(pin)-2)))#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)/* general configuration options */#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)#define S3C2410_GPIO_INPUT (0xFFFFFFF0)#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A *//* configure GPIO ports A..G */#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)/* port A - S3C2410: 22bits, zero in bit X makes pin X output * S3C2400: 18bits, zero in bit X makes pin X output * 1 makes port special function, this is default*/#define S3C2410_GPACON S3C2410_GPIOREG(0x00)#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)#define S3C2400_GPACON S3C2410_GPIOREG(0x00)#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)#define S3C2410_GPA0_OUT (0<<0)#define S3C2410_GPA0_ADDR0 (1<<0)#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)#define S3C2410_GPA1_OUT (0<<1)#define S3C2410_GPA1_ADDR16 (1<<1)#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)#define S3C2410_GPA2_OUT (0<<2)#define S3C2410_GPA2_ADDR17 (1<<2)#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)#define S3C2410_GPA3_OUT (0<<3)#define S3C2410_GPA3_ADDR18 (1<<3)#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)#define S3C2410_GPA4_OUT (0<<4)#define S3C2410_GPA4_ADDR19 (1<<4)#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)#define S3C2410_GPA5_OUT (0<<5)#define S3C2410_GPA5_ADDR20 (1<<5)#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)#define S3C2410_GPA6_OUT (0<<6)#define S3C2410_GPA6_ADDR21 (1<<6)#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)#define S3C2410_GPA7_OUT (0<<7)#define S3C2410_GPA7_ADDR22 (1<<7)#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)#define S3C2410_GPA8_OUT (0<<8)#define S3C2410_GPA8_ADDR23 (1<<8)#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)#define S3C2410_GPA9_OUT (0<<9)#define S3C2410_GPA9_ADDR24 (1<<9)#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)#define S3C2410_GPA10_OUT (0<<10)#define S3C2410_GPA10_ADDR25 (1<<10)#define S3C2400_GPA10_SCKE (1<<10)#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)#define S3C2410_GPA11_OUT (0<<11)#define S3C2410_GPA11_ADDR26 (1<<11)#define S3C2400_GPA11_nCAS0 (1<<11)#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)#define S3C2410_GPA12_OUT (0<<12)#define S3C2410_GPA12_nGCS1 (1<<12)#define S3C2400_GPA12_nCAS1 (1<<12)#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)#define S3C2410_GPA13_OUT (0<<13)#define S3C2410_GPA13_nGCS2 (1<<13)#define S3C2400_GPA13_nGCS1 (1<<13)#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)#define S3C2410_GPA14_OUT (0<<14)#define S3C2410_GPA14_nGCS3 (1<<14)#define S3C2400_GPA14_nGCS2 (1<<14)#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)#define S3C2410_GPA15_OUT (0<<15)#define S3C2410_GPA15_nGCS4 (1<<15)#define S3C2400_GPA15_nGCS3 (1<<15)#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)#define S3C2410_GPA16_OUT (0<<16)#define S3C2410_GPA16_nGCS5 (1<<16)#define S3C2400_GPA16_nGCS4 (1<<16)#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)#define S3C2410_GPA17_OUT (0<<17)#define S3C2410_GPA17_CLE (1<<17)#define S3C2400_GPA17_nGCS5 (1<<17)#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)#define S3C2410_GPA18_OUT (0<<18)#define S3C2410_GPA18_ALE (1<<18)#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)#define S3C2410_GPA19_OUT (0<<19)#define S3C2410_GPA19_nFWE (1<<19)#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)#define S3C2410_GPA20_OUT (0<<20)#define S3C2410_GPA20_nFRE (1<<20)#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)#define S3C2410_GPA21_OUT (0<<21)#define S3C2410_GPA21_nRSTOUT (1<<21)#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)#define S3C2410_GPA22_OUT (0<<22)#define S3C2410_GPA22_nFCE (1<<22)/* 0x08 and 0x0c are reserved on S3C2410 *//* S3C2410: * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. * 00 = input, 01 = output, 10=special function, 11=reserved * S3C2400: * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. * 00 = input, 01 = output, 10=data, 11=special function * bit 0,1 = pin 0, 2,3= pin 1... * * CPBUP = pull up resistor control, 1=disabled, 0=enabled*/#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)/* no i/o pin in port b can have value 3! */#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)#define S3C2410_GPB0_INP (0x00 << 0)#define S3C2410_GPB0_OUTP (0x01 << 0)#define S3C2410_GPB0_TOUT0 (0x02 << 0)#define S3C2400_GPB0_DATA16 (0x02 << 0)#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)#define S3C2410_GPB1_INP (0x00 << 2)#define S3C2410_GPB1_OUTP (0x01 << 2)#define S3C2410_GPB1_TOUT1 (0x02 << 2)#define S3C2400_GPB1_DATA17 (0x02 << 2)#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)#define S3C2410_GPB2_INP (0x00 << 4)#define S3C2410_GPB2_OUTP (0x01 << 4)#define S3C2410_GPB2_TOUT2 (0x02 << 4)#define S3C2400_GPB2_DATA18 (0x02 << 4)#define S3C2400_GPB2_TCLK1 (0x03 << 4)#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)#define S3C2410_GPB3_INP (0x00 << 6)#define S3C2410_GPB3_OUTP (0x01 << 6)#define S3C2410_GPB3_TOUT3 (0x02 << 6)#define S3C2400_GPB3_DATA19 (0x02 << 6)#define S3C2400_GPB3_TXD1 (0x03 << 6)#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)#define S3C2410_GPB4_INP (0x00 << 8)#define S3C2410_GPB4_OUTP (0x01 << 8)#define S3C2410_GPB4_TCLK0 (0x02 << 8)#define S3C2400_GPB4_DATA20 (0x02 << 8)#define S3C2410_GPB4_MASK (0x03 << 8)#define S3C2400_GPB4_RXD1 (0x03 << 8)#define S3C2400_GPB4_MASK (0x03 << 8)#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)#define S3C2410_GPB5_INP (0x00 << 10)#define S3C2410_GPB5_OUTP (0x01 << 10)#define S3C2410_GPB5_nXBACK (0x02 << 10)#define S3C2400_GPB5_DATA21 (0x02 << 10)#define S3C2400_GPB5_nCTS1 (0x03 << 10)#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)#define S3C2410_GPB6_INP (0x00 << 12)#define S3C2410_GPB6_OUTP (0x01 << 12)#define S3C2410_GPB6_nXBREQ (0x02 << 12)#define S3C2400_GPB6_DATA22 (0x02 << 12)#define S3C2400_GPB6_nRTS1 (0x03 << 12)#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)#define S3C2410_GPB7_INP (0x00 << 14)#define S3C2410_GPB7_OUTP (0x01 << 14)#define S3C2410_GPB7_nXDACK1 (0x02 << 14)#define S3C2400_GPB7_DATA23 (0x02 << 14)#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)#define S3C2410_GPB8_INP (0x00 << 16)#define S3C2410_GPB8_OUTP (0x01 << 16)#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)#define S3C2400_GPB8_DATA24 (0x02 << 16)#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)#define S3C2410_GPB9_INP (0x00 << 18)#define S3C2410_GPB9_OUTP (0x01 << 18)#define S3C2410_GPB9_nXDACK0 (0x02 << 18)#define S3C2400_GPB9_DATA25 (0x02 << 18)#define S3C2400_GPB9_I2SSDI (0x03 << 18)#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)#define S3C2410_GPB10_INP (0x00 << 20)#define S3C2410_GPB10_OUTP (0x01 << 20)#define S3C2410_GPB10_nXDRE0 (0x02 << 20)#define S3C2400_GPB10_DATA26 (0x02 << 20)#define S3C2400_GPB10_nSS (0x03 << 20)#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)#define S3C2400_GPB11_INP (0x00 << 22)#define S3C2400_GPB11_OUTP (0x01 << 22)#define S3C2400_GPB11_DATA27 (0x02 << 22)#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)#define S3C2400_GPB12_INP (0x00 << 24)#define S3C2400_GPB12_OUTP (0x01 << 24)#define S3C2400_GPB12_DATA28 (0x02 << 24)#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)#define S3C2400_GPB13_INP (0x00 << 26)#define S3C2400_GPB13_OUTP (0x01 << 26)#define S3C2400_GPB13_DATA29 (0x02 << 26)#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)#define S3C2400_GPB14_INP (0x00 << 28)#define S3C2400_GPB14_OUTP (0x01 << 28)#define S3C2400_GPB14_DATA30 (0x02 << 28)#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)#define S3C2400_GPB15_INP (0x00 << 30)#define S3C2400_GPB15_OUTP (0x01 << 30)#define S3C2400_GPB15_DATA31 (0x02 << 30)#define S3C2410_GPB_PUPDIS(x) (1<<(x))/* Port C consits of 16 GPIO/Special function * * almost identical setup to port b, but the special functions are mostly * to do with the video system's sync/etc.*/#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)#define S3C2410_GPC0_INP (0x00 << 0)#define S3C2410_GPC0_OUTP (0x01 << 0)#define S3C2410_GPC0_LEND (0x02 << 0)#define S3C2400_GPC0_VD0 (0x02 << 0)#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)#define S3C2410_GPC1_INP (0x00 << 2)#define S3C2410_GPC1_OUTP (0x01 << 2)#define S3C2410_GPC1_VCLK (0x02 << 2)#define S3C2400_GPC1_VD1 (0x02 << 2)#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)#define S3C2410_GPC2_INP (0x00 << 4)#define S3C2410_GPC2_OUTP (0x01 << 4)#define S3C2410_GPC2_VLINE (0x02 << 4)#define S3C2400_GPC2_VD2 (0x02 << 4)#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)#define S3C2410_GPC3_INP (0x00 << 6)#define S3C2410_GPC3_OUTP (0x01 << 6)#define S3C2410_GPC3_VFRAME (0x02 << 6)#define S3C2400_GPC3_VD3 (0x02 << 6)#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)#define S3C2410_GPC4_INP (0x00 << 8)#define S3C2410_GPC4_OUTP (0x01 << 8)#define S3C2410_GPC4_VM (0x02 << 8)#define S3C2400_GPC4_VD4 (0x02 << 8)⌨️ 快捷键说明
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