📄 fs453.cpp
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#define FS453_QPR_QK_UO_LSH 3
#define FS453_QPR_QK_GMODE_LSH 1
#define FS453_QPR_QK_PN_LSH 0
//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
//0x00
#define FS453_IHO_IHO_WID 11
//0x02
#define FS453_IVO_IVO_WID 11
//0x04
#define FS453_IHW_IHW_WID 10
//0x06
#define FS453_VSC_VSC_WID 16
//0x08
#define FS453_HSC_HUSC_WID 8
#define FS453_HSC_HDSC_WID 8
//0x0A
#define FS453_BYPASS_B_BYPASS_WID 1
#define FS453_BYPASS_CAC_BYPASS_WID 1
#define FS453_BYPASS_HDS_BYPASS_WID 1
//0x0c
#define FS453_CR_GCC_CK_LVL_WID 1
#define FS453_CR_P656_LVL_WID 1
#define FS453_CR_P656_IN_WID 1
#define FS453_CR_P656_OUT_WID 1
#define FS453_CR_CBAR_480P_WID 1
#define FS453_CR_PAL_NTSCIN_WID 1
#define FS453_CR_SYNC_MS_WID 1
#define FS453_CR_FIFO_CLR_WID 1
#define FS453_CR_CACQ_CLR_WID 1
#define FS453_CR_CDEC_BP_WID 1
#define FS453_CR_NCO_EN_WID 1
#define FS453_CR_SRESET_WID 1
//0x0e
#define FS453_MISC_P_ORDER_WID 1
#define FS453_MISC_BRDG_RST_WID 1
#define FS453_MISC_UIM_E_WID 1
#define FS453_MISC_UV_SWAP_WID 1
#define FS453_MISC_UIM_DEC_WID 1
#define FS453_MISC_UIM_CCLK_WID 1
#define FS453_MISC_UIM_DCLK_WID 1
#define FS453_MISC_UIM_MOD_WID 4
//0x10
#define FS453_NCONL_NCONL_WID 16
#define FS453_NCONH_NCONH_WID 9
//0x14
#define FS453_NCODL_NCODH_WID 16
#define FS453_NCODH_NCODH_WID 9
//0x18
//@@#define FS453_PLLM_PUMPCNTL_PLLG_WID 3
//@@#define FS453_PLLM_PUMPCNTL_PLLM_WID 12
#define FS453_PLLM_PUMPCNTL_PLLM_WID 15
//0x1A
#define FS453_PLLN_PLLN_WID 9
//0x1C
#define FS453_PLL_POSTDIV_PLL_EP_WID 7
#define FS453_PLL_POSTDIV_PLL_IP_WID 7
//0x24
#define FS453_SHP_SHP_WID 5
//0x26
#define FS453_FLK_FLK_WID 5
//0x32
#define FS453_ID_ID_WID 16
//0x38
#define FS453_FIFO_LAT_FIFO_LAT_WID 8
//0x47
#define FS453_MISC_47_CHR_BW_WID 1
#define FS453_MISC_47_COMP_YUV_WID 1
#define FS453_MISC_47_COMP_GAIN_WID 2
//0x48
#define FS453_HSYNC_WID_HSYNC_WID_WID 8
//0x49
#define FS453_BURST_WID_BURST_WID_WID 7
//0x4A
#define FS453_BPORCH_BPORCH_WID 8
//0x4B
#define FS453_CB_BURST_CB_BURST_WID 8
//0x4C
#define FS453_CR_BURST_CR_BURST_WID 8
//0x4E
#define FS453_BLACK_LVL_BLACK_LVL_WID 10
//0x50
#define FS453_BLANK_LVL_BLANK_LVL_WID 10
//0x5E
#define FS453_WHITE_LVL_WHITE_LVL_WID 10
//0x60
#define FS453_CB_GAIN_CB_GAIN_WID 8
//0x62
#define FS453_CR_GAIN_CR_GAIN_WID 8
//0x69
#define FS453_BR_WAY_BR_WAY_WID 5
//0x6C
#define FS453_FR_PORCH_FR_PORCH_WID 6
//0x74
#define FS453_MISC_74_UV_ORDER_WID 1
#define FS453_MISC_74_PAL_MODE_WID 1
#define FS453_MISC_74_CHR_BW_WID 1
#define FS453_MISC_74_INVERT_TOP_WID 1
#define FS453_MISC_74_SYS625_50_WID 1
#define FS453_MISC_74_CH_PH_R_WID 2
#define FS453_MISC_74_VSYNC5_WID 1
//0x75
#define FS453_SYNC_LVL_SYNC_LVL_WID 8
//0x8D
#define FS453_MISC_8D_NOTCH_EN_WID 1
#define FS453_MISC_8D_NOTCH_WD_WID 1
#define FS453_MISC_8D_NOTCH_FREQ_WID 3
//0x92
#define FS453_VID_CNTL0_TOP_FIELD_WID 1
#define FS453_VID_CNTL0_OBIN_USIG_WID 1
#define FS453_VID_CNTL0_PRPB_SYNC_WID 1
#define FS453_VID_CNTL0_VSYNC5_6_WID 1
#define FS453_VID_CNTL0_BLANK_INV_WID 1
#define FS453_VID_CNTL0_FIELD_INV_WID 1
#define FS453_VID_CNTL0_VSYNC_INV_WID 1
#define FS453_VID_CNTL0_HSYNC_INV_WID 1
#define FS453_VID_CNTL0_INT_PROG_WID 1
#define FS453_VID_CNTL0_FIELD_MS_WID 1
#define FS453_VID_CNTL0_SYNC_LVL_WID 1
#define FS453_VID_CNTL0_SYNC_BI_TRI_WID 1
#define FS453_VID_CNTL0_SYNC_ADD_WID 1
#define FS453_VID_CNTL0_MATRIX_BYP_WID 1
#define FS453_VID_CNTL0_VID_MODE_WID 2
//0x9E
#define FS453_DAC_CNTL_DAC_DMUX_WID 2
#define FS453_DAC_CNTL_DAC_CMUX_WID 2
#define FS453_DAC_CNTL_DAC_BMUX_WID 2
#define FS453_DAC_CNTL_DAC_AMUX_WID 2
//0xa0
#define FS453_PWR_MGNT_GTLIO_PD_WID 1
#define FS453_PWR_MGNT_PLL_PD_WID 1
#define FS453_PWR_MGNT_CLKOFF_WID 1
#define FS453_PWR_MGNT_CLK_SOFF_WID 2
#define FS453_PWR_MGNT_DAC_D_LP_WID 1
#define FS453_PWR_MGNT_DAC_C_LP_WID 1
#define FS453_PWR_MGNT_DAC_B_LP_WID 1
#define FS453_PWR_MGNT_DAC_A_LP_WID 1
#define FS453_PWR_MGNT_BGAP_OFF_WID 1
#define FS453_PWR_MGNT_DAC_D_OFF_WID 1
#define FS453_PWR_MGNT_DAC_C_OFF_WID 1
#define FS453_PWR_MGNT_DAC_B_OFF_WID 1
#define FS453_PWR_MGNT_DAC_A_OFF_WID 1
//0xc4
#define FS453_QPR_INITIATE_WID 4
#define FS453_QPR_QK_UIM_WID 2
#define FS453_QPR_QK_OS_WID 2
#define FS453_QPR_QK_YC_IN_WID 1
#define FS453_QPR_QK_FF_WID 1
#define FS453_QPR_QK_OM_WID 2
#define FS453_QPR_QK_UO_WID 1
#define FS453_QPR_QK_GMODE_WID 2
#define FS453_QPR_QK_PN_WID 1
//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------
#define FS453_SET_ENABLE 1
#define FS453_SET_DISABLE 0
//0x0a
#define FS453_BYPASS_B_BYPASS_HD_MODE 1
//0x0C
#define FS453_CR_GCC_CK_LVL_LOW_VOL 1
#define FS453_CR_GCC_CK_LVL_OPENDRAIN 0
#define FS453_CR_P656_LVL_LVTTL 1
#define FS453_CR_P656_LVL_OPENDRAIN 0
//0x0E
#define FS453_MISC_UIM_MOD_M888D 0
#define FS453_MISC_UIM_MOD_M888I 1
#define FS453_MISC_UIM_MOD_M565I 1
#define FS453_MISC_UIM_MOD_M555 2
#define FS453_MISC_UIM_MOD_N888 3
#define FS453_MISC_UIM_MOD_N666 3
#define FS453_MISC_UIM_MOD_N565 3
#define FS453_MISC_UIM_MOD_M444C 4
#define FS453_MISC_UIM_MOD_M444T1 5
#define FS453_MISC_UIM_MOD_M565T2 6
#define FS453_MISC_UIM_MOD_M422 7
#define FS453_MISC_UIM_MOD_N656 8
#define FS453_MISC_UIM_MOD_N601 9
#define FS453_MISC_UIM_MOD_N444 10
//0x47
#define FS453_MISC_47_COMP_YUV_RGB_OUTPUT 0
#define FS453_MISC_47_COMP_YUV_YUV_OUTPUT 1
#define FS453_MISC_47_COMP_GAIN_100 0
#define FS453_MISC_47_COMP_GAIN_25 1
#define FS453_MISC_47_COMP_GAIN_50 2
#define FS453_MISC_47_COMP_GAIN_75 3
//0x47,0x8d
#define FS453_FILTER_BANDWIDTH_NARROW 0
#define FS453_FILTER_BANDWIDTH_WIDE 1
#define FS453_FILTER_BANDWIDTH_EXTRA_WIDE 2
#define FS453_FILTER_BANDWIDTH_ULTRA_WIDE 3
//0x74
#define FS453_MISC_74_CH_PH_R_EVERY_8_FIELDS 0
#define FS453_MISC_74_CH_PH_R_EVERY_4_FIELDS 1
#define FS453_MISC_74_CH_PH_R_EVERY_OTHER_LINES 2
#define FS453_MISC_74_CH_PH_R_ONCE 3
//0x92
#define FS453_VID_CNTL0_TOP_FIELD_IS_LINE1 0
#define FS453_VID_CNTL0_TOP_FIELD_IS_LINE2 1
#define FS453_VID_CNTL0_OBIN_USIG_UNSIGNED 0
#define FS453_VID_CNTL0_OBIN_USIG_OFFSETBIN 1
#define FS453_VID_CNTL0_VSYNC5_6_6HALF_LINES 0
#define FS453_VID_CNTL0_VSYNC5_6_5HALF_LINES 1
#define FS453_VID_CNTL0_VID_MODE_COMPOSIT_SVIDEO 0
#define FS453_VID_CNTL0_VID_MODE_SDTV_YPRPB 1
#define FS453_VID_CNTL0_VID_MODE_SCART 1
#define FS453_VID_CNTL0_VID_MODE_HDTV_YPRPB 2
#define FS453_VID_CNTL0_VID_MODE_VGA_RGB 2
//0x9E
#define FS453_DAC_CNTL_DAC_MUX_SIGNAL0 0
#define FS453_DAC_CNTL_DAC_MUX_SIGNAL1 1
#define FS453_DAC_CNTL_DAC_MUX_SIGNAL2 2
#define FS453_DAC_CNTL_DAC_MUX_SIGNAL3 3
//0xa0
#define FS453_PWR_MGNT_GTLIO_PD_POWERDOWN_MODE 1
#define FS453_PWR_MGNT_GTLIO_PD_NORMAL_MODE 0
#define FS453_PWR_MGNT_PLL_PD_POWERDOWN_MODE 1
#define FS453_PWR_MGNT_PLL_PD_NORMAL_MODE 0
#define FS453_PWR_MGNT_CLK_SOFF_HDTV_CLK_OFF 1
#define FS453_PWR_MGNT_CLK_SOFF_SDTV_CLK_OFF 2
//0xC4
#define FS453_QPR_SET_INITIATE 9
#define FS453_QPR_QK_UIM_RESERVED 0
#define FS453_QPR_QK_UIM_NVIDIA 1
#define FS453_QPR_QK_UIM_INTEL 2
#define FS453_QPR_QK_UIM_NATIONAL 3
#define FS453_QPR_QK_OS_SDTV 0
#define FS453_QPR_QK_OS_480P 1
#define FS453_QPR_QK_OS_720P 2
#define FS453_QPR_QK_OS_1080I 3
#define FS453_QPR_QK_YC_IN_RGB 0
#define FS453_QPR_QK_YC_IN_YCRCB 1
#define FS453_QPR_QK_OM_SVIDEO_COMPOSITE 0
#define FS453_QPR_QK_OM_YPRPB 1
#define FS453_QPR_QK_OM_SCART 2
#define FS453_QPR_QK_OM_VGA 3
#define FS453_QPR_QK_UO_OVERSCAN 0
#define FS453_QPR_QK_UO_UNDERSCAN 1
#define FS453_QPR_QK_GMODE_VGA 0
#define FS453_QPR_QK_GMODE_NTSC_PAL 1
#define FS453_QPR_QK_GMODE_SVGA 2
#define FS453_QPR_QK_GMODE_XGA 3
#define FS453_QPR_QK_PN_NTSC 0
#define FS453_QPR_QK_PN_PAL 1
#define FS453_ID_NUMBER 0xFE05
//-----------------------------------------------------------------------------
// Types
typedef enum
{
FS453_PARAM_PLL_NCONL = 0,
FS453_PARAM_PLL_NCONH,
FS453_PARAM_PLL_NCODL,
FS453_PARAM_PLL_NCODH,
FS453_PARAM_PLL_M,
FS453_PARAM_PLL_N,
FS453_PARAM_PLL_P_IP,
FS453_PARAM_PLL_P_EP,
FS453_PARAM_POSITION_HORIZ,
FS453_PARAM_POSITION_VERTI,
FS453_PARAM_HACTIVE,
FS453_PARAM_SCALE_VERTI,
FS453_PARAM_SCALE_HORIZ_UPSCALE,
FS453_PARAM_SCALE_HORIZ_DOWNSCALE,
FS453_PARAM_UNDERSCALE,
FS453_PARAM_FIFO_LATENCY,
FS453_PARAM_MAX,
}FS453_PARAMETER;
//-----------------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------------
// Local Variables
static HANDLE m_hI2C = NULL; // Driver handle of I2C
static DWORD m_dwFs453CrVal = 0;
typedef DWORD FS453PARAM;
/*
typedef enum{
FS453_TVOUT_MODE_ONTSC_IVGA_RGB565_26400KHZ = 0,
FS453_TVOUT_MODE_ONTSC_IVGA_RGB565_27000KHZ = 1,
FS453_TVOUT_MODE_ONTSC_ID1_VCRCB_27000KHZ = 2,
FS453_PARAM_MAX,
}FS453_TVOUT_MODE;
*/
static FS453PARAM m_Fs453Parameters[TVOUT_MODE_MAX][FS453_PARAM_MAX] =
{
//FS453_TVOUT_MODE_ONTSC_IVGA_RGB565_26400KHZ
{
0,//FS453_PARAM_PLL_NCONL = 0,
0,//FS453_PARAM_PLL_NCONH,
0,//FS453_PARAM_PLL_NCODL,
0,//FS453_PARAM_PLL_NCODH,
0x30F7,//FS453_PARAM_PLL_M,
0x002c,//FS453_PARAM_PLL_N,
0x05,//FS453_PARAM_PLL_P_IP,
0x05,//FS453_PARAM_PLL_P_EP,
0x0058,//FS453_PARAM_POSITION_HORIZ,
0x0018,//FS453_PARAM_POSITION_VERTI,
0x0280,//FS453_PARAM_HACTIVE,
0x0276,//FS453_PARAM_SCALE_VERTI,
0x10,//FS453_PARAM_SCALE_HORIZ_UPSCALE,
0x00,//FS453_PARAM_SCALE_HORIZ_DOWNSCALE,
0,//FS453_PARAM_UNDERSCALE,
0x00A4,//FS453_PARAM_FIFO_LATENCY
},
//FS453_TVOUT_MODE_OPAL_IVGA_RGB565_26400KHZ
{
0,//FS453_PARAM_PLL_NCONL = 0,
0,//FS453_PARAM_PLL_NCONH,
0,//FS453_PARAM_PLL_NCODL,
0,//FS453_PARAM_PLL_NCODH,
0x30F7,//FS453_PARAM_PLL_M,
0x002c,//FS453_PARAM_PLL_N,
0x05,//FS453_PARAM_PLL_P_IP,
0x05,//FS453_PARAM_PLL_P_EP,
0x00A8,//FS453_PARAM_POSITION_HORIZ,
0x0018,//FS453_PARAM_POSITION_VERTI,
0x0280,//FS453_PARAM_HACTIVE,
0x2F07,//FS453_PARAM_SCALE_VERTI,
0x10,//FS453_PARAM_SCALE_HORIZ_UPSCALE,
0x00,//FS453_PARAM_SCALE_HORIZ_DOWNSCALE,
0,//FS453_PARAM_UNDERSCALE,
0x00A4,//FS453_PARAM_FIFO_LATENCY
},
};
//-----------------------------------------------------------------------------
// Local Function
#if (FS453_DEBUGWRITE ==1)
#define Fs453WriteRegister(addr, dat) m_fs453WriteRegisterTest((addr ## _ADDR),(dat),(addr ## _WID))
#else
#define Fs453WriteRegister(addr, dat) m_fs453WriteRegister((addr ## _ADDR),(dat),(addr ## _WID))
#endif
#define Fs453ReadRegister(addr, dat) m_fs453ReadRegister((addr ## _ADDR),(dat),(addr ## _WID))
static BOOL m_fs453WriteRegister(BYTE reg, DWORD * pValue, WORD byteLen);
static BOOL m_fs453ReadRegister(BYTE reg, DWORD * pValue, WORD byteLen);
static void m_SwitchRefPll(void);
static BOOL m_fs453SwReset(void);
static BOOL m_fs453UpdatePLL(void);
static void m_SwitchRefPllSet(void);
static void m_SwitchRefPllGo(void);
//-----------------------------------------------------------------------------
//
// Function: m_fs453WriteRegister
//
// This function write data to the registers in FS453 via I2C control interface.
//
// Parameters:
// BYTE reg - the address of FS453 internal register
// DWORD* pValue - data to write
// WORD byteLen - the byte to write
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
static BOOL m_fs453WriteRegister(BYTE reg, DWORD * pValue, WORD byteLen)
{
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