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MIT的一个数字频综源代码

module: dsynth_acc_with_set2
parameters: double ic double setval
inputs:  double_interp clk double set double in
outputs:  double out
classes: EdgeDetect edge_clk();
static_variables: double out_sample
init: out=ic;
code:
if(set==1)
 {
 out_sample=setval;
 out=out_sample;
 }
else if (edge_clk.inp(clk))
 {
 out_sample=out;
 out=out_sample+in;
 }