wr.map.qmsg

usb 接口芯片isp1581 程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 20 10:33:08 2008 " "Info: Processing started: Thu Mar 20 10:33:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off WR -c WR " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off WR -c WR" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "WR.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file WR.v" { { "Info" "ISGN_ENTITY_NAME" "1 WR " "Info: Found entity 1: WR" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "WR " "Info: Elaborating entity \"WR\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 WR.v(15) " "Warning (10230): Verilog HDL assignment warning at WR.v(15): truncated value with size 32 to match size of target (3)" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 WR.v(26) " "Warning (10230): Verilog HDL assignment warning at WR.v(26): truncated value with size 32 to match size of target (3)" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[6\]~reg0 data_in GND " "Warning: Reduced register \"AD\[6\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "AD\[5\]~reg0 High " "Info: Power-up level of register \"AD\[5\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[5\]~reg0 data_in VCC " "Warning: Reduced register \"AD\[5\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[4\]~reg0 data_in GND " "Warning: Reduced register \"AD\[4\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "AD\[3\]~reg0 High " "Info: Power-up level of register \"AD\[3\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[3\]~reg0 data_in VCC " "Warning: Reduced register \"AD\[3\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[2\]~reg0 data_in GND " "Warning: Reduced register \"AD\[2\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "AD\[1\]~reg0 High " "Info: Power-up level of register \"AD\[1\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[1\]~reg0 data_in VCC " "Warning: Reduced register \"AD\[1\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "AD\[0\]~reg0 High " "Info: Power-up level of register \"AD\[0\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[0\]~reg0 data_in VCC " "Warning: Reduced register \"AD\[0\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "AD\[7\]~reg0 High " "Info: Power-up level of register \"AD\[7\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "AD\[7\]~reg0 data_in VCC " "Warning: Reduced register \"AD\[7\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~2 nCS~reg0 " "Info: Duplicate register \"always0~2\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~4 nCS~reg0 " "Info: Duplicate register \"always0~4\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~6 nCS~reg0 " "Info: Duplicate register \"always0~6\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~8 nCS~reg0 " "Info: Duplicate register \"always0~8\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~10 nCS~reg0 " "Info: Duplicate register \"always0~10\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~12 nCS~reg0 " "Info: Duplicate register \"always0~12\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~14 nCS~reg0 " "Info: Duplicate register \"always0~14\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "always0~1 nCS~reg0 " "Info: Duplicate register \"always0~1\" merged to single register \"nCS~reg0\", power-up level changed" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "WR_high\[0\] cs_low\[0\] " "Info: Duplicate register \"WR_high\[0\]\" merged to single register \"cs_low\[0\]\"" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "WR_high\[1\] cs_low\[1\] " "Info: Duplicate register \"WR_high\[1\]\" merged to single register \"cs_low\[1\]\"" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "WR_high\[2\] cs_low\[2\] " "Info: Duplicate register \"WR_high\[2\]\" merged to single register \"cs_low\[2\]\"" {  } { { "WR.v" "" { Text "E:/课题/ISP1581 verilog hdl/写寄存器/WR.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "16 " "Info: Implemented 16 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 20 10:33:09 2008 " "Info: Processing ended: Thu Mar 20 10:33:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}