8019.h

是TCPIP程序

#define RUNT    	60
                        //smallest legal size packet, no fcs
#define GIANT	        1514
                        //largest legal size packet, no fcs
#define ETHER_ADDR_LEN	6
                        //Ethernet address length.

#define TX_PAGES	6
#define NE_START_PG	0X40
                        //First page of TX buffer
#define NE_STOP_PG	0X60
                        //Last page + 1 of RX Ring
#define RX_START_PG	NE_START_PG + TX_PAGES
#define RX_CURR_PG	RX_START_PG + 1


#define EN_CMD		XBYTE[0X8000]
                        //The command register (for all pages)
#define EN_DATA 	XBYTE[0X8010]
                        //remote DMA Port (for all pages)
#define EN_RESET	XBYTE[0X801F]
                        //Reset Port (for all pages)

//Register accessed at EN_CMD, the RTL8019 base addr
#define EN_STOP		0X01
                        //Stop and reset the chip
#define EN_START	0X02
                        //Start the chip, clear reset
#define EN_TRANS	0X04
                        //Transmit a frame
#define EN_RREAD	0X08
                        //Remote read
#define EN_RWRITE	0X10
                        //Remote write
#define EN_NODMA	0X20
                        //Remote DMA
#define EN_PAGE0	0X00
                        //Select page chip registers
#define EN_PAGE1	0X40
                        //using the two high-order bits
#define EN_PAGE2	0X80
#define EN_PAGE3	0XC0

//Page 0 register offsets
#define EN0_CLDALO	XBYTE[0X8001]
                        //RD Low byte of current local dma addr
#define EN0_STARTPG	XBYTE[0X8001]
                        //WR Starting page of ring buffer
#define EN0_CLDAHI	XBYTE[0X8002]
                        //RD High byte of current local dma addr
#define EN0_STOPPG	XBYTE[0X8002]
                        //WR Ending page +1 of ring buffer
#define EN0_BOUNDARY	XBYTE[0X8003]
                        //RD/WR Boundary page of ring buffer
#define EN0_TSR		XBYTE[0X8004]
                        //RD Transmit status reg
#define EN0_TPSR	XBYTE[0X8004]
                        //WR Transmit starting page
#define EN0_NCR		XBYTE[0X8005]
                        //RD Number of collision reg
#define EN0_TCNTLO	XBYTE[0X8005]
                        //WR Low  byte of tx byte count
#define EN0_FIFO	XBYTE[0X8006]
                        //RD FIFO
#define EN0_TCNTHI	XBYTE[0X8006]
                        //WR High byte of tx byte count
#define EN0_ISR		XBYTE[0X8007]
                        //RD/WR Interrupt status reg
#define EN0_CRDALO	XBYTE[0X8008]
                        //RD low byte of current remote dma address
#define EN0_RSARLO	XBYTE[0X8008]
                        //WR Remote start address reg 0
#define EN0_CRDAHI	XBYTE[0X8009]
                        //RD high byte, current remote dma address
#define EN0_RSARHI	XBYTE[0X8009]
                        //WR Remote start address reg 1
#define EN0_RCNTLO	XBYTE[0X800a]
                        //WR Remote byte count reg
#define EN0_RCNTHI	XBYTE[0X800b]
                        //WR Remote byte count reg
#define EN0_RSR		XBYTE[0X800c]
                        //RD RX status reg
#define EN0_RXCR	XBYTE[0X800c]
                        //WR RX configuration reg
#define EN0_TXCR	XBYTE[0X800d]
                        //WR TX configuration reg
#define EN0_COUNTER0	XBYTE[0X800d]
                        //RD Rcv alignment error counter
#define EN0_DCFG	XBYTE[0X800e]
                        //WR Data configuration reg
#define EN0_COUNTER1	XBYTE[0X800e]
                        //RD Rcv CRC error counter
#define EN0_IMR		XBYTE[0X800f]
                        //WR Interrupt mask reg
#define EN0_COUNTER2	XBYTE[0X800f]
                        //RD Rcv missed frame error counter


//Bits in EN0_TSR - Transmitted packet status
#define ENTSR_PTX	0X01
                        //Packet transmitted without error
#define ENTSR_ND	0X02
                        //The transmit wasn't deferred.
#define ENTSR_COL	0X04
                        //The transmit collided at least once.
#define ENTSR_ABT	0X08
                        //The transmit collided 16 times, and was deferred.
#define ENTSR_CRS	0X10
                        //The carrier sense was lost.
#define ENTSR_FU	0X20
                        //The collision detect "heartbeat" signal was lost.
#define ENTSR_OWC	0X80


//Bits in EN0_ISR - Interrupt status register
#define ENISR_RX	0X01
                        //Receiver, no error
#define ENISR_TX	0X02
                        //Transmitter, no error
#define ENISR_RX_ERR	0X04
                        //Receiver, with error
#define ENISR_TX_ERR	0X08
                        //Transmitter, with error
#define ENISR_OVER	0X10
                        //Receiver overwrote the ring
#define ENISR_COUNTERS	0X20
                        //Counters need emptying
#define ENISR_RDC	0X40
                        //remote dma complete
#define ENISR_RESET	0X80
                        //Reset completed
#define ENISR_ALL	0X3f
                        //Interrupts we will enable

//Bits in EN0_RSR and received packet status byte
#define ENRSR_RXOK	0X01
                        //Received a good packet
#define ENRSR_CRC	0X02
                        //CRC error
#define ENRSR_FAE	0X04
                        //frame alignment error
#define ENRSR_FO	0X08
                        //FIFO overrun
#define ENRSR_MPA	0X10
                        //missed pkt
#define ENRSR_PHY	0X20
                        //physical/multicase address
#define ENRSR_DIS	0X40
                        //receiver disable. set in monitor mode
#define ENRSR_DEF	0X80


//Bits in EN0_RXCR - RX configuration reg
#define ENRXCR_CRC	0X01
                        //Save error pkts
#define ENRXCR_RUNT	0X02
                        //Accept runt pkt
#define ENRXCR_BCST	0X04
                        //Accept broadcasts
#define ENRXCR_MULTI	0X08
                        //Multicast (if pass filter)
#define ENRXCR_PROMP	0X10
                        //Promiscuous physical addresses
#define ENRXCR_MON	0X20
                        //Monitor mode (no packets rcvd)

//Bits in EN0_TXCR - TX configuration reg
#define ENTXCR_CRC	0X01
                        //inhibit CRC, do not append crc
#define ENTXCR_LOOP	0X02
                        //set internal loopback mode
#define ENTXCR_LB01	0X06
                        //encoded loopback control
#define ENTXCR_ATD	0X08
                        //auto tx disable
#define ENTXCR_OFST	0X10
                        //collision offset enable

//Bits in EN0_DCFG - Data config register
#define ENDCFG_WTS	0X00
                        //byte transfer mode selection
#define ENDCFG_BOS	0X02
                        //byte order selection

                        //0: MD15-8, LSB on MD7-0

                        //1: MSB on MD7-0, LSB on MD15-8
#define ENDCFG_LAS	0X04
                        //long addr selection (must be set to zero)
#define ENDCFG_BMS	0X08
                        //loopback select
                        //0: Loopback mode select. Bits 1 and 2 of the
                        //EN0_TXCR must also be programmed for Loopback
                        //1: Normal operation
#define ENDCFG_ARM	0X10
                        //autoinitialize remote
#define ENDCFG_FT00	0X00
                        //fifo treshold
#define ENDCFG_FT01	0X20
#define ENDCFG_FT10	0X40
#define ENDCFG_FT11	0X60
                        //Page 1 register offsets
#define EN1_PHYS	0X8001
                        //RD/WR This board's physical enet addr
#define EN1_CURPAG	XBYTE[0X8007]
                        //RD/WR Current memory page
#define EN1_MULT	0X8008
                        //RD/WR Multicast filter mask array (8 bytes)

#define EN_RBUF_STAT	 0
                        //Received frame status
#define EN_RBUF_NXT_PG	 1
                        //Page after this frame
#define EN_RBUF_SIZE_LO	 2
                        //Length of this frame
#define EN_RBUF_SIZE_HI	 3
                        //Length of this frame
#define SIZE_OF_8019_HDR 4
                        //size of 8019 specific packet header

#define PKT_DEST	        0
#define PKT_SRC	                6
#define PKT_TYPE	        12
#define SIZE_OF_ETH_PKT_HDR	14