pin_pout.rpt

是128*64程序

P22      : INPUT;
QK1      : INPUT;
QK2      : INPUT;
QK3      : INPUT;
QK4      : INPUT;
QK5      : INPUT;
QK6      : INPUT;
RXT      : INPUT;
TXD      : INPUT;

-- Node name is 'AD' 
-- Equation name is 'AD', type is output 
AD       = !_LC2_F33;

-- Node name is 'A0' 
-- Equation name is 'A0', type is output 
A0       =  _LC5_C34;

-- Node name is 'A1' 
-- Equation name is 'A1', type is output 
A1       =  _LC7_C34;

-- Node name is 'A2' 
-- Equation name is 'A2', type is output 
A2       =  _LC1_C34;

-- Node name is 'A3' 
-- Equation name is 'A3', type is output 
A3       =  _LC2_D26;

-- Node name is 'A4' 
-- Equation name is 'A4', type is output 
A4       =  _LC3_D26;

-- Node name is 'A5' 
-- Equation name is 'A5', type is output 
A5       =  _LC5_D26;

-- Node name is 'A6' 
-- Equation name is 'A6', type is output 
A6       =  _LC7_D26;

-- Node name is 'A7' 
-- Equation name is 'A7', type is output 
A7       =  _LC1_D26;

-- Node name is 'DK0~1' 
-- Equation name is 'DK0~1', location is LC1_E4, type is buried.
-- synthesized logic cell 
_LC1_E4  = LCELL( P10);

-- Node name is 'DK0' 
-- Equation name is 'DK0', type is output 
DK0      =  _LC1_E4;

-- Node name is 'DK1~1' 
-- Equation name is 'DK1~1', location is LC1_E16, type is buried.
-- synthesized logic cell 
_LC1_E16 = LCELL( P11);

-- Node name is 'DK1' 
-- Equation name is 'DK1', type is output 
DK1      =  _LC1_E16;

-- Node name is 'DK2~1' 
-- Equation name is 'DK2~1', location is LC8_E5, type is buried.
-- synthesized logic cell 
_LC8_E5  = LCELL( P12);

-- Node name is 'DK2' 
-- Equation name is 'DK2', type is output 
DK2      =  _LC8_E5;

-- Node name is 'DK3~1' 
-- Equation name is 'DK3~1', location is LC4_F14, type is buried.
-- synthesized logic cell 
_LC4_F14 = LCELL( P13);

-- Node name is 'DK3' 
-- Equation name is 'DK3', type is output 
DK3      =  _LC4_F14;

-- Node name is 'DK4~1' 
-- Equation name is 'DK4~1', location is LC6_F36, type is buried.
-- synthesized logic cell 
_LC6_F36 = LCELL( P22);

-- Node name is 'DK4' 
-- Equation name is 'DK4', type is output 
DK4      =  _LC6_F36;

-- Node name is 'QK7~1' 
-- Equation name is 'QK7~1', location is LC2_A12, type is buried.
-- synthesized logic cell 
_LC2_A12 = LCELL( DK7);

-- Node name is 'QK7' 
-- Equation name is 'QK7', type is output 
QK7      =  _LC2_A12;

-- Node name is 'RAM' 
-- Equation name is 'RAM', type is output 
RAM      = !_LC2_F36;

-- Node name is ':30' 
-- Equation name is '_LC1_D26', type is buried 
_LC1_D26 = DFFE( P07, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':32' 
-- Equation name is '_LC7_D26', type is buried 
_LC7_D26 = DFFE( P06, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':34' 
-- Equation name is '_LC5_D26', type is buried 
_LC5_D26 = DFFE( P05, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':36' 
-- Equation name is '_LC3_D26', type is buried 
_LC3_D26 = DFFE( P04, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':38' 
-- Equation name is '_LC2_D26', type is buried 
_LC2_D26 = DFFE( P03, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':40' 
-- Equation name is '_LC1_C34', type is buried 
_LC1_C34 = DFFE( P02, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':42' 
-- Equation name is '_LC7_C34', type is buried 
_LC7_C34 = DFFE( P01, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':44' 
-- Equation name is '_LC5_C34', type is buried 
_LC5_C34 = DFFE( P00, !ALE,  VCC,  VCC,  VCC);

-- Node name is ':227' 
-- Equation name is '_LC2_F33', type is buried 
!_LC2_F33 = _LC2_F33~NOT;
_LC2_F33~NOT = LCELL( _EQ001);
  _EQ001 =  P21
         #  P22
         #  P20;

-- Node name is ':376' 
-- Equation name is '_LC2_F36', type is buried 
!_LC2_F36 = _LC2_F36~NOT;
_LC2_F36~NOT = LCELL( _EQ002);
  _EQ002 = !P20
         #  P21
         #  P22;



Project Information                 e:\eda\jheda1k30\lced12864drv\pin_pout.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,338K