📄 pin_pout.rpt
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Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 8
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 3/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 5/0
E: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 4/0
Total: 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 1 3 0 2 16/0
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
31 - - F -- INPUT ^ 0 0 0 8 ALE
100 - - A -- INPUT ^ 0 0 0 1 DK7
102 - - A -- INPUT ^ 0 0 0 1 P00
117 - - - 08 INPUT ^ 0 0 0 1 P01
118 - - - 09 INPUT ^ 0 0 0 1 P02
119 - - - 13 INPUT ^ 0 0 0 1 P03
120 - - - 14 INPUT ^ 0 0 0 1 P04
121 - - - 17 INPUT ^ 0 0 0 1 P05
130 - - - 22 INPUT ^ 0 0 0 1 P06
131 - - - 23 INPUT ^ 0 0 0 1 P07
27 - - E -- INPUT ^ 0 0 0 1 P10
28 - - E -- INPUT ^ 0 0 0 1 P11
29 - - E -- INPUT ^ 0 0 0 1 P12
30 - - F -- INPUT ^ 0 0 0 1 P13
32 - - F -- INPUT ^ 0 0 0 2 P20
33 - - F -- INPUT ^ 0 0 0 2 P21
36 - - - 36 INPUT ^ 0 0 0 3 P22
83 - - E -- INPUT ^ 0 0 0 0 QK1
86 - - E -- INPUT ^ 0 0 0 0 QK2
87 - - E -- INPUT ^ 0 0 0 0 QK3
88 - - D -- INPUT ^ 0 0 0 0 QK4
89 - - D -- INPUT ^ 0 0 0 0 QK5
90 - - D -- INPUT ^ 0 0 0 0 QK6
80 - - F -- INPUT ^ 0 0 0 0 RXT
79 - - F -- INPUT ^ 0 0 0 0 TXD
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - - 34 OUTPUT 0 1 0 0 AD
17 - - C -- OUTPUT 0 1 0 0 A0
18 - - C -- OUTPUT 0 1 0 0 A1
19 - - D -- OUTPUT 0 1 0 0 A2
20 - - D -- OUTPUT 0 1 0 0 A3
21 - - D -- OUTPUT 0 1 0 0 A4
22 - - D -- OUTPUT 0 1 0 0 A5
23 - - D -- OUTPUT 0 1 0 0 A6
26 - - E -- OUTPUT 0 1 0 0 A7
97 - - C -- OUTPUT 0 1 0 0 DK0
92 - - D -- OUTPUT 0 1 0 0 DK1
95 - - C -- OUTPUT 0 1 0 0 DK2
96 - - C -- OUTPUT 0 1 0 0 DK3
98 - - B -- OUTPUT 0 1 0 0 DK4
91 - - D -- OUTPUT 0 1 0 0 QK7
37 - - - 35 OUTPUT 0 1 0 0 RAM
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - E 04 LCELL s 1 0 1 0 DK0~1
- 1 - E 16 LCELL s 1 0 1 0 DK1~1
- 8 - E 05 LCELL s 1 0 1 0 DK2~1
- 4 - F 14 LCELL s 1 0 1 0 DK3~1
- 6 - F 36 LCELL s 1 0 1 0 DK4~1
- 2 - A 12 LCELL s 1 0 1 0 QK7~1
- 1 - D 26 DFFE 2 0 1 0 :30
- 7 - D 26 DFFE 2 0 1 0 :32
- 5 - D 26 DFFE 2 0 1 0 :34
- 3 - D 26 DFFE 2 0 1 0 :36
- 2 - D 26 DFFE 2 0 1 0 :38
- 1 - C 34 DFFE 2 0 1 0 :40
- 7 - C 34 DFFE 2 0 1 0 :42
- 5 - C 34 DFFE 2 0 1 0 :44
- 2 - F 33 OR2 ! 3 0 1 0 :227
- 2 - F 36 OR2 ! 3 0 1 0 :376
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
B: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 3/144( 2%) 3/ 72( 4%) 3/ 72( 4%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
D: 6/144( 4%) 2/ 72( 2%) 5/ 72( 6%) 3/16( 18%) 7/16( 43%) 0/16( 0%)
E: 3/144( 2%) 0/ 72( 0%) 1/ 72( 1%) 6/16( 37%) 1/16( 6%) 0/16( 0%)
F: 4/144( 2%) 0/ 72( 0%) 1/ 72( 1%) 6/16( 37%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 ALE
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** EQUATIONS **
ALE : INPUT;
DK7 : INPUT;
P00 : INPUT;
P01 : INPUT;
P02 : INPUT;
P03 : INPUT;
P04 : INPUT;
P05 : INPUT;
P06 : INPUT;
P07 : INPUT;
P10 : INPUT;
P11 : INPUT;
P12 : INPUT;
P13 : INPUT;
P20 : INPUT;
P21 : INPUT;
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