📄 pin_pout.rpt
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Project Information e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 02/12/2005 17:37:47
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PIN_POUT
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
pin_pout EP1K30TC144-3 25 16 0 0 0 % 16 0 %
User Pins: 25 16 0
Project Information e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'TXD' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'RXT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'QK1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
pin_pout@38 AD
pin_pout@31 ALE
pin_pout@17 A0
pin_pout@18 A1
pin_pout@19 A2
pin_pout@20 A3
pin_pout@21 A4
pin_pout@22 A5
pin_pout@23 A6
pin_pout@26 A7
pin_pout@97 DK0
pin_pout@92 DK1
pin_pout@95 DK2
pin_pout@96 DK3
pin_pout@98 DK4
pin_pout@100 DK7
pin_pout@102 P00
pin_pout@117 P01
pin_pout@118 P02
pin_pout@119 P03
pin_pout@120 P04
pin_pout@121 P05
pin_pout@130 P06
pin_pout@131 P07
pin_pout@27 P10
pin_pout@28 P11
pin_pout@29 P12
pin_pout@30 P13
pin_pout@32 P20
pin_pout@33 P21
pin_pout@36 P22
pin_pout@83 QK1
pin_pout@86 QK2
pin_pout@87 QK3
pin_pout@88 QK4
pin_pout@89 QK5
pin_pout@90 QK6
pin_pout@91 QK7
pin_pout@37 RAM
pin_pout@80 RXT
pin_pout@79 TXD
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
***** Logic for device 'pin_pout' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S V S S S S S S S S
E E E E E E E E E V E E E C E E V E E E E E E
R R R R R R R R R C R R R C R R C R R R R R R
V V V V V G V V V V C V V P P G V I G G G G V P P P P P V C V V V V V V
E E E E E N E E E E I E E 0 0 N E N N N N N E 0 0 0 0 0 E I E E E E E E
D D D D D D D D D D O D D 7 6 D D T D D D D D 5 4 3 2 1 D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | P00
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | DK7
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | DK4
RESERVED | 12 97 | DK0
RESERVED | 13 96 | DK3
RESERVED | 14 95 | DK2
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
A0 | 17 92 | DK1
A1 | 18 91 | QK7
A2 | 19 EP1K30TC144-3 90 | QK6
A3 | 20 89 | QK5
A4 | 21 88 | QK4
A5 | 22 87 | QK3
A6 | 23 86 | QK2
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
A7 | 26 83 | QK1
P10 | 27 82 | RESERVED
P11 | 28 81 | RESERVED
P12 | 29 80 | RXT
P13 | 30 79 | TXD
ALE | 31 78 | RESERVED
P20 | 32 77 | ^MSEL0
P21 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
P22 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R A R G R R R R V R R R R V R G V G G G G G R R V R R R R G R R R R V R
A D E N E E E E C E E E E C E N C N N N N N E E C E E E E N E E E E C E
M S D S S S S C S S S S C S D C D D D D D S S C S S S S D S S S S C S
E E E E E I E E E E I E I E E I E E E E E E E E I E
R R R R R O R R R R N R N R R O R R R R R R R R O R
V V V V V V V V V T V T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\eda\jheda1k30\lced12864drv\pin_pout.rpt
pin_pout
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C34 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
D26 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
E4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
E5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
E16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
F14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
F33 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F36 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 41/96 ( 42%)
Total logic cells used: 16/1728 ( 0%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 1.25/4 ( 31%)
Total fan-in: 20/6912 ( 0%)
Total input pins required: 25
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