gt64_diag.c

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////////////////////////////////////////////////////////////////
// File - GT64_DIAG.C
//
// o A simple diagnostics program that lets you access the
//   Marvell GT64 registers and local memory. 
// o This program is meant to be used as an example for using the GT64_LIB.H API,
//   you may use it as a skeleton for your driver, or 'cut & paste' parts
//   of it into your device driver code.
// 
////////////////////////////////////////////////////////////////

#include "../../../include/windrvr.h"
#include "../lib/gt64_lib.h"
#include "../../../samples/shared/pci_diag_lib.h"
#include <stdio.h>

// input of command from user
static char line[256];

void GT64_EditReg(GT64_HANDLE hGT)
{
    struct 
    {
        CHAR *name;
        DWORD dwOffset;
        DWORD dwVal;
    } fields[160];
    struct
    {
        CHAR *name;
        int iPosition;
    } group[20];

    int cmd, cmd2;
    int i = 0;
    int j = 0;
    int iGroupNum;
    int iFieldsNum;
    BOOL f111 = hGT->gt64Ver==GT64_VERSION_64111;
    BOOL f120 = hGT->gt64Ver==GT64_VERSION_64120;
    BOOL f130 = hGT->gt64Ver==GT64_VERSION_64130;

    // CPU/Local Master Interface Configuration
    group[j].name ="CPU/Local Master Interface Configuration"; group[j++].iPosition = i;
    fields[i].name ="CPU/Local Master Interface Configuration"; fields[i++].dwOffset = 0x000;
    if (f120 || f130) 
    {
        fields[i].name ="Multi-GT Register"; fields[i++].dwOffset = 0x120;
    }
    // Processor Address Space
    group[j].name ="Processor Address Space"; group[j++].iPosition = i;
    fields[i].name ="RAS[1:0] Low Decode Address"; fields[i++].dwOffset = 0x008;
    fields[i].name ="RAS[1:0] High Decode Address"; fields[i++].dwOffset = 0x010;
    fields[i].name ="RAS[3:2] Low Decode Address"; fields[i++].dwOffset = 0x018;
    fields[i].name ="RAS[3:2] High Decode Address"; fields[i++].dwOffset = 0x020;
    fields[i].name ="CS[2:0] Low Decode Address"; fields[i++].dwOffset = 0x028;
    fields[i].name ="CS[2:0] High Decode Address"; fields[i++].dwOffset = 0x030;
    fields[i].name ="CS[3] & Boot CS Low Decode Address"; fields[i++].dwOffset = 0x038;
    fields[i].name ="CS[3] & Boot CS High Decode Address"; fields[i++].dwOffset = 0x040;
    fields[i].name ="PCI I/O Low Decode Address"; fields[i++].dwOffset = 0x048;
    fields[i].name ="PCI I/O High Decode Address"; fields[i++].dwOffset = 0x050;
    fields[i].name ="PCI Memory 0 Low Decode Address"; fields[i++].dwOffset = 0x058;
    fields[i].name ="PCI Memory 0 High Decode Address"; fields[i++].dwOffset = 0x060;
    fields[i].name ="Internal Space Decode"; fields[i++].dwOffset = 0x068;
    fields[i].name ="Bus Error Address Low Processor"; fields[i++].dwOffset = 0x070;
    fields[i].name ="Read Only 0"; fields[i++].dwOffset = 0x078;
    fields[i].name ="PCI Memory 1 Low Decode Address"; fields[i++].dwOffset = 0x080;
    fields[i].name ="PCI Memory 1 High Decode Address"; fields[i++].dwOffset = 0x088;
    if (f120 || f130)
    {
        fields[i].name ="PCI_1 I/O Low Decode Address"; fields[i++].dwOffset = 0x090;
        fields[i].name ="PCI_1 I/O High Decode Address"; fields[i++].dwOffset = 0x098;
        fields[i].name ="PCI_1 Memory 0 Low Decode Address"; fields[i++].dwOffset = 0x0a0;
        fields[i].name ="PCI_1 Memory 0 High Decode Address"; fields[i++].dwOffset = 0x0a8;
        fields[i].name ="PCI_1 Memory 1 Low Decode Address"; fields[i++].dwOffset = 0x0b0;
        fields[i].name ="PCI_1 Memory 1 High Decode Address"; fields[i++].dwOffset = 0x0b8;
        fields[i].name ="SCS[1:0]* Address Remap"; fields[i++].dwOffset = 0x0d0;
        fields[i].name ="SCS[3:2]* Address Remap"; fields[i++].dwOffset = 0x0d8;
        fields[i].name ="CS[2:0]* Remap"; fields[i++].dwOffset = 0x0e0;
        fields[i].name ="CS[3]* & Boot CS* Remap"; fields[i++].dwOffset = 0x0e8;
        fields[i].name ="PCI_0 IO Remap"; fields[i++].dwOffset = 0x0f0;
        fields[i].name ="PCI_0 Memory 0 Remap"; fields[i++].dwOffset = 0x0f8;
        fields[i].name ="PCI_0 Memory 1 Remap"; fields[i++].dwOffset = 0x100;
        fields[i].name ="PCI_1 IO Remap"; fields[i++].dwOffset = 0x108;
        fields[i].name ="PCI_1 Memory 0 Remap"; fields[i++].dwOffset = 0x110;
        fields[i].name ="PCI_1 Memory 1 Remap"; fields[i++].dwOffset = 0x118;
        //CPU Sync Barrier
        group[j].name ="CPU Sync Barrier"; group[j++].iPosition = i;
        fields[i].name ="PCI_0 Sync Barrier Virtual Register"; fields[i++].dwOffset = 0x0c0;
        fields[i].name ="PCI_1 Sync Barrier Virtual Register"; fields[i++].dwOffset = 0x0c8;
    }
    //DRAM and Device Address Space
    group[j].name ="DRAM and Device Address Space"; group[j++].iPosition = i;
    fields[i].name ="RAS[0] Low Decode Address"; fields[i++].dwOffset = 0x400;
    fields[i].name ="RAS[0] High Decode Address"; fields[i++].dwOffset = 0x404;
    fields[i].name ="RAS[1] Low Decode Address"; fields[i++].dwOffset = 0x408;
    fields[i].name ="RAS[1] High Decode Address"; fields[i++].dwOffset = 0x40c;
    fields[i].name ="RAS[2] Low Decode Address"; fields[i++].dwOffset = 0x410;
    fields[i].name ="RAS[2] High Decode Address"; fields[i++].dwOffset = 0x414;
    fields[i].name ="RAS[3] Low Decode Address"; fields[i++].dwOffset = 0x418;
    fields[i].name ="RAS[3] High Decode Address"; fields[i++].dwOffset = 0x41c;
    fields[i].name ="CS[0] Low Decode Address"; fields[i++].dwOffset = 0x420;
    fields[i].name ="CS[0] High Decode Address"; fields[i++].dwOffset = 0x424;
    fields[i].name ="CS[1] Low Decode Address"; fields[i++].dwOffset = 0x428;
    fields[i].name ="CS[1] High Decode Address"; fields[i++].dwOffset = 0x42c;
    fields[i].name ="CS[2] Low Decode Address"; fields[i++].dwOffset = 0x430;
    fields[i].name ="CS[2] High Decode Address"; fields[i++].dwOffset = 0x434;
    fields[i].name ="CS[3] Low Decode Address"; fields[i++].dwOffset = 0x438;
    fields[i].name ="CS[3] High Decode Address"; fields[i++].dwOffset = 0x43c;
    fields[i].name ="Boot CS Low Decode Address"; fields[i++].dwOffset = 0x440;
    fields[i].name ="Boot CS High Decode Address"; fields[i++].dwOffset = 0x444;
    fields[i].name ="Address Decode Error"; fields[i++].dwOffset = 0x470;
    //DRAM Configuration
    group[j].name ="DRAM Configuration"; group[j++].iPosition = i;
    if (f111)
    {
        fields[i].name ="DRAM Configuration"; fields[i++].dwOffset = 0x448;
    }
    else
    {
        fields[i].name ="SDRAM Bank0 Parameters"; fields[i++].dwOffset = 0x44c;
        fields[i].name ="SDRAM Bank1 Parameters"; fields[i++].dwOffset = 0x450;
        fields[i].name ="SDRAM Bank2 Parameters"; fields[i++].dwOffset = 0x454;
        fields[i].name ="SDRAM Bank3 Parameters"; fields[i++].dwOffset = 0x458;
    }
    //DRAM Parameters
    group[j].name ="DRAM Parameters"; group[j++].iPosition = i;
    fields[i].name ="DRAM Bank0 Parameters"; fields[i++].dwOffset = 0x44c;
    fields[i].name ="DRAM Bank1 Parameters"; fields[i++].dwOffset = 0x450;
    fields[i].name ="DRAM Bank2 Parameters"; fields[i++].dwOffset = 0x454;
    fields[i].name ="DRAM Bank3 Parameters"; fields[i++].dwOffset = 0x458;
    //Device Parameters
    group[j].name ="Device Parameters"; group[j++].iPosition = i;
    fields[i].name ="Device Bank0 Parameters"; fields[i++].dwOffset = 0x45c;
    fields[i].name ="Device Bank1 Parameters"; fields[i++].dwOffset = 0x460;
    fields[i].name ="Device Bank2 Parameters"; fields[i++].dwOffset = 0x464;
    fields[i].name ="Device Bank3 Parameters"; fields[i++].dwOffset = 0x468;
    fields[i].name ="Device Boot Bank Parameters"; fields[i++].dwOffset = 0x46c;
    if (f130)
    {
        // ECC
        group[j].name ="ECC"; group[j++].iPosition = i;
        fields[i].name ="ECC Upper_Data"; fields[i++].dwOffset = 0x480;
        fields[i].name ="ECC Lower Data"; fields[i++].dwOffset = 0x484;
        fields[i].name ="ECC From Memory"; fields[i++].dwOffset = 0x488;
        fields[i].name ="ECC Calculated"; fields[i++].dwOffset = 0x48c;
        fields[i].name ="ECC Error Report"; fields[i++].dwOffset = 0x490;
    }
    //DMA Record
    group[j].name ="DMA Record"; group[j++].iPosition = i;
    fields[i].name ="Channel 0 DMA Byte Count"; fields[i++].dwOffset = 0x800;
    fields[i].name ="Channel 1 DMA Byte Count"; fields[i++].dwOffset = 0x804;
    fields[i].name ="Channel 2 DMA Byte Count"; fields[i++].dwOffset = 0x808;
    fields[i].name ="Channel 3 DMA Byte Count"; fields[i++].dwOffset = 0x80c;
    fields[i].name ="Channel 0 DMA Source Address"; fields[i++].dwOffset = 0x810;
    fields[i].name ="Channel 1 DMA Source Address"; fields[i++].dwOffset = 0x814;
    fields[i].name ="Channel 2 DMA Source Address"; fields[i++].dwOffset = 0x818;
    fields[i].name ="Channel 3 DMA Source Address"; fields[i++].dwOffset = 0x81c;
    fields[i].name ="Channel 0 DMA Destination Address"; fields[i++].dwOffset = 0x820;
    fields[i].name ="Channel 1 DMA Destination Address"; fields[i++].dwOffset = 0x824;
    fields[i].name ="Channel 2 DMA Destination Address"; fields[i++].dwOffset = 0x828;
    fields[i].name ="Channel 3 DMA Destination Address"; fields[i++].dwOffset = 0x82c;
    fields[i].name ="Channel 0 Next Record Pointer"; fields[i++].dwOffset = 0x830;
    fields[i].name ="Channel 1 Next Record Pointer"; fields[i++].dwOffset = 0x834;
    fields[i].name ="Channel 2 Next Record Pointer"; fields[i++].dwOffset = 0x838;
    fields[i].name ="Channel 3 Next Record Pointer"; fields[i++].dwOffset = 0x83c;
    if (f120 || f130)
    {
        fields[i].name ="Channel 0 Current Descriptor Pointer"; fields[i++].dwOffset = 0x870;
        fields[i].name ="Channel 1 Current Descriptor Pointer"; fields[i++].dwOffset = 0x874;
        fields[i].name ="Channel 2 Current Descriptor Pointer"; fields[i++].dwOffset = 0x878;
        fields[i].name ="Channel 3 Current Descriptor Pointer"; fields[i++].dwOffset = 0x87c;
    }
    //DMA Channel Control
    group[j].name ="DMA Channel Control"; group[j++].iPosition = i;
    fields[i].name ="Channel 0 Control"; fields[i++].dwOffset = 0x840;
    fields[i].name ="Channel 1 Control"; fields[i++].dwOffset = 0x844;
    fields[i].name ="Channel 2 Control"; fields[i++].dwOffset = 0x848;
    fields[i].name ="Channel 3 Control"; fields[i++].dwOffset = 0x84c;
    //DMA Arbiter
    group[j].name ="DMA Arbiter"; group[j++].iPosition = i;
    fields[i].name ="Arbiter Control"; fields[i++].dwOffset = 0x860;
    //Timer Counter
    group[j].name ="Timer Counter"; group[j++].iPosition = i;
    fields[i].name ="Timer /Counter 0"; fields[i++].dwOffset = 0x850;
    fields[i].name ="Timer /Counter 1"; fields[i++].dwOffset = 0x854;
    fields[i].name ="Timer /Counter 2"; fields[i++].dwOffset = 0x858;
    fields[i].name ="Timer /Counter 3"; fields[i++].dwOffset = 0x85c;
    fields[i].name ="Timer /Counter Control"; fields[i++].dwOffset = 0x864;
    //PCI Internal
    group[j].name ="PCI Internal"; group[j++].iPosition = i;
    if (f111)
    {
        fields[i].name ="Command"; fields[i++].dwOffset = 0xc00;
        fields[i].name ="Time Out & Retry"; fields[i++].dwOffset = 0xc04;
        fields[i].name ="RAS[1:0] Bank Size"; fields[i++].dwOffset = 0xc08;
        fields[i].name ="RAS[3:2] Bank Size"; fields[i++].dwOffset = 0xc0c;
        fields[i].name ="CS[2:0] Bank Size"; fields[i++].dwOffset = 0xc10;
        fields[i].name ="CS[3] & Boot CS Bank Size"; fields[i++].dwOffset = 0xc14;
        fields[i].name ="SErr Mask"; fields[i++].dwOffset = 0xc28;
        fields[i].name ="Interrupt Acknowledge"; fields[i++].dwOffset = 0xc34;
        fields[i].name ="Base Address Registers Enable"; fields[i++].dwOffset = 0xc3c;
        fields[i].name ="Configuration Address"; fields[i++].dwOffset = 0xcf8;
        fields[i].name ="Configuration Data"; fields[i++].dwOffset = 0xcfc;
    }
    else
    {
        fields[i].name ="PCI_0 Command"; fields[i++].dwOffset = 0xc00;
        fields[i].name ="PCI_1 Command"; fields[i++].dwOffset = 0xc80;
        fields[i].name ="PCI_0 Time Out & Retry"; fields[i++].dwOffset = 0xc04;
        fields[i].name ="PCI_1 Time Out & Retry"; fields[i++].dwOffset = 0xc84;
        fields[i].name ="PCI_0 SCS[1:0]* Bank Size"; fields[i++].dwOffset = 0xc08;
        fields[i].name ="PCI_1 SCS[1:0]* Bank Size"; fields[i++].dwOffset = 0xc88;
        fields[i].name ="PCI_0 SCS[3:2]* Bank Size"; fields[i++].dwOffset = 0xc0c;
        fields[i].name ="PCI_1 SCS[3:2]* Bank Size"; fields[i++].dwOffset = 0xc8c;
        fields[i].name ="PCI_0 CS[2:0]* Bank Size"; fields[i++].dwOffset = 0xc10;
        fields[i].name ="PCI_1 CS[2:0]* Bank Size"; fields[i++].dwOffset = 0xc90;
        fields[i].name ="PCI_0 CS[3]* & Boot CS* Bank Size"; fields[i++].dwOffset = 0xc14;
        fields[i].name ="PCI_1 CS[3]* & Boot CS* Bank Size"; fields[i++].dwOffset = 0xc94;
        fields[i].name ="PCI_0 Base Address Registers