ver1-optimized.chp

来自「基于XILINX的内嵌POWERPC的处理器的串行通讯的应用源代码.」· CHP 代码 · 共 141 行

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Chip ver1-Optimized
===================

Summary Information:
--------------------
Type: Optimized implementation
Source: ver1, up to date
Status: 0 errors, 243 warnings, 0 messages
Export: exported after last optimization

Target Information:
-------------------
Vendor: Xilinx
Family: SPARTAN
Device: S10TQ144
Speed: -4

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: High
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 64
Number of latches: 0

Chip Design Hierarchy:
----------------------
UART: defined in c:\phili\fndtn\miniuart\miniuart.vhd

Primitive reference count:
--------------------------
BUFG          4
FDC           9
FDCE         46
FMAP         61
GND          60
HMAP          4
IBUF          6
IFDX          8
INV           3
IPAD          2
OBUF         11
OFDX          1
VCC           1

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00   99.40     BR_Clk_I_BUFGed      
 -1       -1       -1      -1000.00  100.00     N295_BUFGed          
 -1       -1       -1      -1000.00  100.00     N294_BUFGed          
 -1       -1       -1      -1000.00   52.63     WB_CLK_I_BUFGed      

Timing Groups:
--------------
                                                                             
                                                                             
Name                           Description                                   
...........................................................................
(I)                            Input ports                                   
(O)                            Output ports                                  
(RC,BR_Clk_I_BUFGed)           Clocked by rising edge of BR_Clk_I_BUFGed     
(RC,N295_BUFGed)               Clocked by rising edge of N295_BUFGed         
(RC,N294_BUFGed)               Clocked by rising edge of N294_BUFGed         
(RC,WB_CLK_I_BUFGed)           Clocked by rising edge of WB_CLK_I_BUFGed     

Timing Path Groups:
-------------------
                                                          Required  Estimated 
                                                          Delay     Delay     
From                         To                           (ns)      (ns)      
..........................................................................
(I)                          (O)                           20.00     13.45    
(I)                          (RC,BR_Clk_I_BUFGed)          20.00      9.20    
(I)                          (RC,WB_CLK_I_BUFGed)          20.00     19.00    
(RC,BR_Clk_I_BUFGed)         (O)                           20.00     13.73    
(RC,BR_Clk_I_BUFGed)         (RC,BR_Clk_I_BUFGed)          20.00     10.06    
(RC,N295_BUFGed)             (RC,BR_Clk_I_BUFGed)          20.00      2.89    
(RC,N294_BUFGed)             (O)                           20.00     11.81    
(RC,WB_CLK_I_BUFGed)         (RC,BR_Clk_I_BUFGed)          20.00      3.54    

Input Port Timing:
------------------
                               Required   Estimated                            
Port                           Delay      Slack                                
Name                           (ns)       (ns)       To-Group                  
...........................................................................
WB_CLK_I                        19.90      19.90     (RC,BR_Clk_I_BUFGed)      
WB_RST_I                        13.93      13.93     (RC,BR_Clk_I_BUFGed)      
WB_ADR_I<1>                      6.55       6.55     (RC,BR_Clk_I_BUFGed)      
WB_ADR_I<0>                      6.55       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<7>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<6>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<5>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<4>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<3>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<2>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<1>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_DAT_I<0>                      1.00       1.00     (RC,BR_Clk_I_BUFGed)      
WB_WE_I                         15.47      15.47     (RC,BR_Clk_I_BUFGed)      
WB_STB_I                         9.15       9.15     (RC,BR_Clk_I_BUFGed)      
BR_Clk_I                        19.90      19.90     (RC,BR_Clk_I_BUFGed)      
RxD_PAD_I                       10.80      10.80     (RC,BR_Clk_I_BUFGed)      

Output Port Timing:
-------------------
                               Required   Estimated                            
Port                           Delay      Slack                                
Name                           (ns)       (ns)       From-Group                
...........................................................................
WB_DAT_O<7>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<6>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<5>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<4>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<3>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<2>                     20.00       6.55     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<1>                     20.00       7.85     (RC,BR_Clk_I_BUFGed)      
WB_DAT_O<0>                     20.00       6.27     (RC,BR_Clk_I_BUFGed)      
WB_ACK_O                        20.00       9.15     (RC,BR_Clk_I_BUFGed)      
IntTx_O                         20.00       7.57     (RC,BR_Clk_I_BUFGed)      
IntRx_O                         20.00       9.49     (RC,BR_Clk_I_BUFGed)      
TxD_PAD_O                       20.00      12.07     (RC,BR_Clk_I_BUFGed)      

Critical Path Timing:
---------------------
                Arrival    Required                                          
Cell            Time       Time       Fanout                                 
Type            (ns)       (ns)       Count   Pin-Name                       
........................................................................
IFDX             19.00      20.00      10     /ver1-Optimized/TxData_reg<7>/C 
IFDX              0.00       1.00       1     /ver1-Optimized/TxData_reg<7>/D 
port              0.00       1.00       1     /ver1-Optimized/WB_DAT_I<7>