l1h.s

uCOS-II ports on Tensilica HiFi330 core.

/* l1h.S -- User and Kernel Vector Exception Handlers
 *		and level-one interrupt dispatchers
 *
 * This code is taken from example code in the Xtensa Microprocessor
 * Programmer's Guide.
 *
 * WARNING:  It is highly unlikely that this code works as is on your
 *	particular Xtensa processor configuration.  It is hardcoded
 *	for the specific processor configuration used for the
 *	examples in the Xtensa Microprocessor Programmer's Guide.
 *	(The example code did not use the Xtensa HAL to address this
 *	portability issue, for clarity's sake.)  Getting it to work
 *	on another processor configuration requires some modifications.
 */

/*
 * Copyright (c) 2003-2005 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

/*
  LevelOneHandlers.S

  Handle the user and kernel exceptions.
*/
#include <xtensa/coreasm.h>

	.data
	.global	intMasking
	.align	4
intMasking:
	.word	0xFFFFFFFF	// interrupt level mask
	.word	0x00000000	// individual enable mask
#define INT_LEVEL_MASK		0	// offset to the level mask
#define INT_ENABLE_MASK		4	// offset to the enable mask

#define FRAME_SIZE 124
	
	.data
	.align 4
.global userStackPtr
userStackPtr:
	.word 0
	
.global newUserStackPtr
newUserStackPtr:
	.word 0

	.align  16
.global intStackBase
.global intStackEnd
intStackBase:
	.space  8192, 0
intStackEnd:
	.space  16, 0
intStackStart:

.global intHandlers
intHandlers:
	.word   L1_int0_extlevel
	.word   L1_int1_extlevel
	.word   L1_int2_extlevel
	.word   L1_int3_extlevel
	.word   L1_int4_extlevel
	.word   L1_int5_extlevel
	.word   L1_int6_timer0
	.word   L1_int7_software
	.word   L2_int8_extlevel
	.word   L3_int9_extlevel
	.word   L3_int10_timer1
	.word   L3_int11_software
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled
	.word   intUnhandled

	.text
	.align 4
.global _UserExceptionHandler
_UserExceptionHandler:
	rsr     a3, EXCCAUSE
	beqi    a3, EXCCAUSE_LEVEL1INTERRUPT, handleInt
	rsr     a3, EXCSAVE_1
	break   1, 1

handleInt:
	addi    a3, a1, -FRAME_SIZE

saveIntRegs:
	s32i    a0, a3, 0
	s32i    a1, a3, 4
	s32i    a2, a3, 8
	s32i    a4, a3, 16
	s32i    a5, a3, 20
	s32i    a6, a3, 24
	s32i    a7, a3, 28
	s32i    a8, a3, 32
	s32i    a9, a3, 36
	s32i    a10, a3, 40
	s32i    a11, a3, 44
	s32i    a12, a3, 48
	s32i    a13, a3, 52
	s32i    a14, a3, 56
	s32i    a15, a3, 60
	rsr     a2, EXCSAVE_1
	s32i    a2, a3, 12
	
#if XCHAL_HAVE_LOOPS	
	rsr     a2, LBEG
	s32i    a2, a3, 64
	rsr     a2, LEND
	s32i    a2, a3, 68
	rsr     a2, LCOUNT
	s32i    a2, a3, 72
#endif
	
	rsr     a2, SAR
	s32i    a2, a3, 76
	rsr     a2, PS
	s32i    a2, a3, 80
	rsr     a2, EPC_1
	s32i    a2, a3, 84
	movi    a2, 0
	
#if XCHAL_HAVE_LOOPS	
	wsr     a2, LCOUNT
#endif
	
	isync

moveToStack:
	movi    a2, userStackPtr
	s32i    a3, a2, 0
	movi    a2, newUserStackPtr
	s32i    a3, a2, 0

	addi    a2, a1, -16
	movi    a1, intStackEnd

	l32i    a0, a2, 0
	s32i    a0, a1, 0
	l32i    a0, a2, 4
	s32i    a0, a1, 4
	l32i    a0, a2, 8
	s32i    a0, a1, 8
	l32i    a0, a2, 12
	s32i    a0, a1, 12

	addi    a1, a1, 16
invokeIntHandler:

	movi    a0, intMasking
	l32i    a2, a0, INT_LEVEL_MASK
	s32i    a2, a3, 88

	rsr     a2, INTERRUPT
	rsr     a3, INTENABLE
	and     a2, a2, a3
	beqz    a2, spurious
	neg     a3, a2
	and     a2, a3, a2

	//rsil  a3, LOCKOUTLEVEL
	movi    a3, ~XCHAL_INTLEVEL1_MASK
	addi    a2, a2, -1
	or      a3, a3, a2
	addi    a2, a2, 1
	s32i    a3, a0, INT_LEVEL_MASK

	l32i    a0, a0, INT_ENABLE_MASK
	and     a3, a3, a0
	wsr     a3, INTENABLE

	movi    a0, userStackPtr
	l32i    a0, a0, 0
	l32i    a0, a0, 0

	movi    a3, PS_WOE_MASK
	wsr     a3, PS
	rsync

	find_ls_one a4, a2

	movi    a3, intHandlers
	addx4   a4, a4, a3
	l32i    a4, a4, 0

	callx4  a4

returnFromInterrupt:

	movi    a3, userStackPtr
	l32i    a3, a3, 0
	l32i    a4, a3, 80
	wsr     a4, PS
	rsync

	movi    a5, intMasking
	l32i    a2, a3, 88
	//rsil  a4, LOCKOUTLEVEL
	s32i    a2, a5, INT_LEVEL_MASK
	l32i    a5, a5, INT_ENABLE_MASK
	and     a2, a2, a5
	wsr     a2, INTENABLE

	movi    a2, intStackEnd

	l32i    a0, a2, 0
	s32i    a0, a3, FRAME_SIZE - 16
	l32i    a0, a2, 4
	s32i    a0, a3, FRAME_SIZE - 12
	l32i    a0, a2, 8
	s32i    a0, a3, FRAME_SIZE - 8
	l32i    a0, a2, 12
	s32i    a0, a3, FRAME_SIZE - 4

arRestore:
	l32i    a4, a3, 16
	l32i    a5, a3, 20
	l32i    a6, a3, 24
	l32i    a7, a3, 28
	l32i    a8, a3, 32
	l32i    a9, a3, 36
	l32i    a10, a3, 40
	l32i    a11, a3, 44
	l32i    a12, a3, 48
	l32i    a13, a3, 52
	l32i    a14, a3, 56
	l32i    a15, a3, 60

	movi    a2, userStackPtr
	movi    a1, newUserStackPtr
	l32i    a0, a2, 0
	l32i    a1, a1, 0
	beq     a0, a1, noSwitch
doSwitch:
	s32i    a1, a2, 0

	l32i    a1, a3, 4
	call0   xthal_window_spill_nw

	movi    a3, userStackPtr
	l32i    a3, a3, 0
	j       arRestore       

noSwitch:
spurious:

	l32i    a2, a3, 80
	wsr     a2, PS
	rsync

	l32i    a0, a3, 84
	wsr     a0, EPC_1
	l32i    a0, a3, 76
	wsr     a0, SAR

#if XCHAL_HAVE_LOOPS	
	l32i    a0, a3, 64
	wsr     a0, LBEG
	l32i    a0, a3, 68
	wsr     a0, LEND
	l32i    a0, a3, 72
	wsr     a0, LCOUNT
#endif
	
	isync

	l32i    a0, a3, 0
	l32i    a1, a3, 4
	l32i    a2, a3, 8
	l32i    a3, a3, 12

	rfe

.global _KernelExceptionHandler
_KernelExceptionHandler:
	rsr     a3, EXCCAUSE
	 beqi    a3, EXCCAUSE_LEVEL1INTERRUPT, nestedHandleInt
	break   1, 1

nestedHandleInt:
	addi    a3, a1, -(FRAME_SIZE + 20)

nestedSaveIntRegs:      
	s32i    a0, a3, 0 + 20
	s32i    a1, a3, 4 + 20
	s32i    a2, a3, 8 + 20
	s32i    a4, a3, 16 + 20
	s32i    a5, a3, 20 + 20
	s32i    a6, a3, 24 + 20
	s32i    a7, a3, 28 + 20
	s32i    a8, a3, 32 + 20
	s32i    a9, a3, 36 + 20
	s32i    a10, a3, 40 + 20
	s32i    a11, a3, 44 + 20
	s32i    a12, a3, 48 + 20
	s32i    a13, a3, 52 + 20
	s32i    a14, a3, 56 + 20
	s32i    a15, a3, 60 + 20
	rsr     a2, EXCSAVE_1
	s32i    a2, a3, 12 + 20

#if XCHAL_HAVE_LOOPS	
	rsr     a2, LBEG
	s32i    a2, a3, 64 + 20
	rsr     a2, LEND
	s32i    a2, a3, 68 + 20
	rsr     a2, LCOUNT
	s32i    a2, a3, 72 + 20
#endif
	
	rsr     a2, SAR
	s32i    a2, a3, 76 + 20
	rsr     a2, PS
	s32i    a2, a3, 80 + 20
	rsr     a2, EPC_1
	s32i    a2, a3, 84 + 20

nestedMoveToStack:
	l32i    a1, a3, (FRAME_SIZE + 20) - 16
	s32i    a1, a3, 0
	l32i    a1, a3, (FRAME_SIZE + 20) - 12
	s32i    a1, a3, 4
	l32i    a1, a3, (FRAME_SIZE + 20) - 8
	s32i    a1, a3, 8
	l32i    a1, a3, (FRAME_SIZE + 20) - 4
	s32i    a1, a3, 12

	addi    a1, a3, 16

nestedInvokeIntHandler:
	movi    a0, intMasking
	l32i    a2, a0, INT_LEVEL_MASK
	s32i    a2, a3, 88 + 20

	rsr     a2, INTERRUPT
	rsr     a3, INTENABLE
	and     a2, a2, a3
	beqz    a2, nestedSpurious
	neg     a3, a2
	and     a2, a3, a2

	//rsil  a3, LOCKOUTLEVEL
	movi    a3, ~XCHAL_INTLEVEL1_MASK
	addi    a2, a2, -1
	or      a3, a3, a2
	addi    a2, a2, 1
	s32i    a3, a0, INT_LEVEL_MASK

	l32i    a0, a0, INT_ENABLE_MASK
	and     a3, a3, a0
	wsr     a3, INTENABLE

	l32i    a0, a1, (FRAME_SIZE + 20) - 16 + 0

	movi    a3, PS_WOE_MASK
	wsr     a3, PS
	rsync

	find_ls_one a4, a2

	movi    a3, intHandlers
	addx4   a4, a4, a3
	l32i    a4, a4, 0

	callx4  a4

nestedReturnFromInterrupt:
	addi    a3, a1, -16
	l32i    a4, a3, 80 + 20
	wsr     a4, PS
	rsync

	l32i    a1, a3, 0
	s32i    a1, a3, (FRAME_SIZE + 20) - 16
	l32i    a1, a3, 4
	s32i    a1, a3, (FRAME_SIZE + 20) - 12
	l32i    a1, a3, 8
	s32i    a1, a3, (FRAME_SIZE + 20) - 8
	l32i    a1, a3, 12      
	s32i    a1, a3, (FRAME_SIZE + 20) - 4

	movi    a5, intMasking
	l32i    a2, a3, 88 + 20
	//rsil  a4, LOCKOUTLEVEL
	s32i    a2, a5, INT_LEVEL_MASK
	l32i    a5, a5, INT_ENABLE_MASK
	and     a2, a2, a5
	wsr     a2, INTENABLE

nestedSpurious:
	l32i    a0, a3, 84 + 20
	wsr     a0, EPC_1
	l32i    a0, a3, 76 + 20
	wsr     a0, SAR

#if XCHAL_HAVE_LOOPS	
	l32i    a0, a3, 64 + 20
	wsr     a0, LBEG
	l32i    a0, a3, 68 + 20
	wsr     a0, LEND
	l32i    a0, a3, 72 + 20
	wsr     a0, LCOUNT
#endif
	
	isync

	l32i    a0, a3, 0 + 20
	l32i    a1, a3, 4 + 20
	l32i    a2, a3, 8 + 20
	l32i    a4, a3, 16 + 20
	l32i    a5, a3, 20 + 20
	l32i    a6, a3, 24 + 20
	l32i    a7, a3, 28 + 20
	l32i    a8, a3, 32 + 20
	l32i    a9, a3, 36 + 20
	l32i    a10, a3, 40 + 20
	l32i    a11, a3, 44 + 20
	l32i    a12, a3, 48 + 20
	l32i    a13, a3, 52 + 20
	l32i    a14, a3, 56 + 20
	l32i    a15, a3, 60 + 20
	l32i    a3, a3, 12 + 20

	rfe