interrupts.h

uCOS-II ports on Tensilica HiFi330 core.

/* interrupts.h -- Interrupt related definitions
 *
 * This code is taken from example code in the Xtensa Microprocessor
 * Programmer's Guide.
 *
 * WARNING:  It is highly unlikely that this code works as is on your
 *	particular Xtensa processor configuration.  It is hardcoded
 *	for the specific processor configuration used for the
 *	examples in the Xtensa Microprocessor Programmer's Guide.
 *	(The example code did not use the Xtensa HAL to address this
 *	portability issue, for clarity's sake.)  Getting it to work
 *	on another processor configuration requires some modifications.
 */

/*
 * Copyright (c) 2003-2005 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

#ifndef _XTSTR
# define _XTSTR(x) # x
# define XTSTR(x) _XTSTR(x)
#endif

#define INT_LEVEL_MASK		0
#define INT_ENABLE_MASK		4

static __inline__ unsigned int enable_ints(unsigned int mask)
{
    extern unsigned int intMasking[2];
    unsigned int ret;
    unsigned int new_intenable;

    __asm__ __volatile__( 
	"rsil    a15, 1                 \n\t"
	"l32i    %0,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
	"or      %1, %0, %2             \n\t"
	"s32i    %1,%3,"XTSTR(INT_ENABLE_MASK)" \n\t"
	"l32i    %2,%3,"XTSTR(INT_LEVEL_MASK)" \n\t"
	"and     %1,%1,%2               \n\t"
	"wsr     %1,"XTSTR(INTENABLE)"  \n\t"
	"wsr     a15, "XTSTR(PS)"       \n\t"
	"rsync                          \n\t"
	: "=&a" (ret), "=&a" (new_intenable)
	: "a" (mask), "a" (intMasking)
	: "a15"
	);
    return ret;
}

static __inline__ unsigned int read_interrupt()
{
    unsigned int interrupt;

    __asm__ __volatile__ ( 
	"rsr     %0, "XTSTR(INTERRUPT)
	: "=a" (interrupt) 
	);
    return interrupt;
}