reset.s

uCOS-II ports on Tensilica HiFi330 core.

/* reset.S -- Reset Vector
 *
 * This code is taken from example code in the Xtensa Microprocessor
 * Programmer's Guide.
 *
 * WARNING:  It is highly unlikely that this code works as is on your
 *	particular Xtensa processor configuration.  It is hardcoded
 *	for the specific processor configuration used for the
 *	examples in the Xtensa Microprocessor Programmer's Guide.
 *	(The example code did not use the Xtensa HAL to address this
 *	portability issue, for clarity's sake.)  Getting it to work
 *	on another processor configuration requires some modifications.
 */

/*
 * Copyright (c) 2003-2005 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

#include <xtensa/coreasm.h>
#include <xtensa/simcall.h>

	.global _ResetVector

	.section        .ResetVector.text, "ax"
	.align  4
_ResetVector:
	j       Reset           // jump around literal pool


	.literal_position  // tells assembler place literals here

	.align  4
Reset:
	movi    a0, 0
	wsr     a0, INTENABLE

    wsr     a0, IBREAKA_0
    wsr     a0, IBREAKA_1
    wsr     a0, DBREAKA_0
    wsr     a0, DBREAKA_1    
	wsr     a0, DBREAKC_0
	wsr     a0, DBREAKC_1
    wsr     a0, IBREAKENABLE
    
    wsr     a0, ICOUNT
	wsr     a0, ICOUNTLEVEL
	isync

	rsil    a1, XCHAL_DEBUGLEVEL - 1

	wsr     a0, CCOUNT
	wsr     a0, WINDOWBASE
	rsync

	movi    a1, 1
	wsr     a1, WINDOWSTART

	ssai    0

   //Level-1 interrupt
	wsr     a0, EXCSAVE_1
	wsr     a0, EPC_1
	wsr     a0, EXCCAUSE

    //Medium priority interrupts
	wsr     a0, EPC_2
	wsr     a0, EPS_2
	wsr     a0, EXCSAVE_2

	wsr     a0, EPC_3
	wsr     a0, EPS_3
	wsr     a0, EXCSAVE_3

    //High priority interrupts
	wsr     a0, EPC_4
	wsr     a0, EPS_4
	wsr     a0, EXCSAVE_4

	wsr     a0, EPC_5       
	wsr     a0, EPS_5
	wsr     a0, EXCSAVE_5
	
	//Debug EPC, EPS and EXCSAVE
    wsr     a0, EPC_6       
	wsr     a0, EPS_6
	wsr     a0, EXCSAVE_6
	
	//NMI EPC, EPS and EXCSAVE
	wsr     a0, EPC_7       
	wsr     a0, EPS_7
	wsr     a0, EXCSAVE_7
	
	//3 timers
	wsr     a0, CCOMPARE_0
	wsr     a0, CCOMPARE_1
	wsr     a0, CCOMPARE_2

	movi    a2, XCHAL_INTTYPE_MASK_EXTERN_EDGE | XCHAL_INTTYPE_MASK_SOFTWARE
	wsr     a2, INTCLEAR

#if XCHAL_HAVE_CP
	wsr     a0, BR
	wsr     a0, CPENABLE
#endif
	movi    a2, XCHAL_DEBUGLEVEL - 1
	wsr     a2, PS
	rsync

	movi    a5, 0xE0000000
	movi    a4, 2
	movi    a3, 0
	j       3f
2:  sub     a3, a3, a5
3:  wdtlb   a4, a3
	witlb   a4, a3
	bne     a3, a5, 2b
	isync

#if (XCHAL_ICACHE_SIZE != 0)

#if (XCHAL_ICACHE_SIZE == 8192)   //212GP and 330HiFi
	movi    a2, 64
#elif (XCHAL_ICACHE_SIZE == 16384)  //232L and 570T	
	movi    a2, 128
#endif

	movi    a3, 0
	loop    a2, .L0
	iiu     a3, 0
	iiu     a3, 32
	iiu     a3, 64
	iiu     a3, 96
	addi    a3, a3, 128
.L0:

#ifdef PROC_PCC_570T
	movi    a2, 64
#else	  
	movi    a2, 32
#endif

	movi    a3, 0	
	loop    a2, .L1
	iii     a3, 0     
	iii     a3, 32 
	iii     a3, 64  
	iii     a3, 96 
	addi    a3, a3, 128
.L1:
	isync
#endif

#if (XCHAL_DCACHE_SIZE != 0)

#if (XCHAL_DCACHE_SIZE == 8192)   //212GP and 330HiFi
	movi    a2, 64
#elif (XCHAL_DCACHE_SIZE == 16384)  //232L and 570T	
	movi    a2, 128
#endif

	movi    a3, 0
	loop    a2, .L2
	diu     a3, 0
	diu     a3, 32
	diu     a3, 64
	diu     a3, 96
	addi    a3, a3, 128
.L2:

#ifdef PROC_PCC_570T
	movi    a2, 64
#else	  
	movi    a2, 32
#endif

	movi    a3, 0
	loop    a2, .L3
	dii     a3, 0
	dii     a3, 32
	dii     a3, 64
	dii     a3, 96
	addi    a3, a3, 128
.L3:
	dsync
#endif

	.macro  set_access_mode am
	movi    a4, \am
	wdtlb   a4, a3
	witlb   a4, a3
	.endm

	// Turn caches on for regions 0x40000000 and 0x60000000
      	  // Disable all accesses for 0, 0x00000000, and 0xE0000000
	// Leave all other regions unchanged (i.e bypassed for devices)


	movi    a3, 0          
	set_access_mode 15
	
	movi    a3, 0x40000000  // ROM
	set_access_mode 1
	
	movi    a3, 0x60000000  // RAM
	set_access_mode 1

	movi    a3, 0xE0000000
	set_access_mode 15


	movi    a2, _rom_store_table
	beqz    a2, unpackdone

unpack:
	l32i    a3, a2, 0       // start vaddr
	l32i    a4, a2, 4       // end vaddr
	l32i    a5, a2, 8       // store vaddr
	bltu    a3, a4, unpack1
	bnez    a3, unpacknext
	bnez    a5, unpacknext
	j       unpackdone

unpack1:
	l32i    a6, a5, 0
	addi    a5, a5, 4
	s32i    a6, a3, 0
	addi    a3, a3, 4
	bltu    a3, a4, unpack1

unpacknext:
	addi    a2, a2, 12
	j       unpack

unpackdone:
	movi    sp, __stack

	movi    a2, PS_WOE_MASK | PS_PROGSTACK_MASK
	wsr     a2, PS
	rsync

#ifdef BSS_SLOW
	movi    a8, _bss_start
	movi    a10, _bss_end
	sub     a11, a10, a8
	srli    a11, a11, 2

	movi    a9, 0
#if XCHAL_HAVE_LOOPS	
    loopnez a11, zerodone
#else
	beqz a11, zerodone
branch_zero:
#endif	
	s32i    a9, a8, 0
	addi    a8, a8, 4
#if !XCHAL_HAVE_LOOPS
    addi    a11, a11, -1
    bnez    a11, branch_zero
#endif		
zerodone:
#else
	movi    a8, _bss_start
	movi    a10, _bss_end
	sub     a11, a10, a8
	slli    a12, a11, 28
	srli    a12, a12, 30

	movi    a9, 0
#if XCHAL_HAVE_LOOPS	
	loopnez a12, zerodone_fourbyte
#else
    beqz    a12, zerodone_fourbyte
branch_4byte:    
#endif
	s32i    a9, a8, 0
	addi    a8, a8, 4
#if !XCHAL_HAVE_LOOPS
    addi    a12, a12, -1
    bnez    a12, branch_4byte
#endif	
zerodone_fourbyte:

	srli    a11, a11, 4
	
#if XCHAL_HAVE_LOOPS		
	loopnez a11, zerodone_16byte
#else
    beqz    a11, zerodone_16byte
branch_16byte:	
#endif	
	s32i    a9, a8, 0
	s32i    a9, a8, 4
	s32i    a9, a8, 8
	s32i    a9, a8, 12
	addi    a8, a8, 16
#if !XCHAL_HAVE_LOOPS
    addi    a11, a11, -1
    bnez    a11, branch_16byte
#endif		
zerodone_16byte:
#endif
callmain:
	movi    a0, 0
	movi    a6, 0   // clear argc
	movi    a7, 0   // clear argv
	movi    a8, 0   // clear envp
	movi    a4, main
	callx4  a4

reset_exit:
	movi    a2, SYS_exit
	simcall