debugexceptionvectorhandler.s

uCOS-II ports on Tensilica HiFi330 core.

/*
 * DebugExceptionVectorHandler.S -- Debug Exception Handler
 */
/* $Id $ */
/*
 * Customer ID=4654; Build=0x116b0; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

#include <xtensa/config/specreg.h>
#include <xtensa/coreasm.h>
#ifdef SIMULATOR
#include <xtensa/simcall.h>
#endif


#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS

// Imports
//	none

	.text
	.align 4
	.globl	_DebugExceptionFromVector
_DebugExceptionFromVector:
	rsr	a0, EXCSAVE_6	// restore a0

# ifdef SIMULATOR
	//  In the simulator, let the debugger (if any) handle the debug exception,
	//  or simply stop the simulation:
	wsr	a2, EXCSAVE_6
	movi	a2, SYS_gdb_enter_sktloop
	simcall					// have ISS handle the debug exception
# else

	//  Returning will likely cause execution to come right back here, so don't:
#  ifndef DEBUG_RETURN_ON_ERROR
1:	j	1b		// infinite loop
#  endif
	rfi	6

# endif /*!SIMULATOR*/

#endif /* XCHAL_HAVE_DEBUG */