internal.h

uCOS-II ports on Tensilica HiFi330 core.

#ifndef XT_INTERNAL_H
#define XT_INTERNAL_H

#define XTOS_SAVE_ALL_MAC16

/*  If we have the NSAU instruction, ordering of interrupts is reversed in _xtos_interrupt_table[]:  */
#if XCHAL_HAVE_NSA
# define MAPINT(n)	((XCHAL_NUM_INTERRUPTS-1)-(n))
	.macro	mapint  an
	neg	\an, \an
	addi	\an, \an, XCHAL_NUM_INTERRUPTS-1
	.endm
#else /* no NSA */
# define MAPINT(n)	(n)
	.macro	mapint  an
	.endm
#endif


	//  Save LOOP and MAC16 registers, if configured, to the exception stack
	//  frame pointed to by address register \esf, using \aa and \ab as temporaries.
	//
	//  Only two temp registers required for this code to be optimal (no interlocks) in both
	//  T10xx (Athens) and Xtensa LX microarchitectures (both 5 and 7 stage pipes):
	//
	.macro	save_loops_mac16	esf, aa, ab
#if XCHAL_HAVE_LOOPS
	rsr	\aa, LCOUNT
	rsr	\ab, LBEG
	s32i	\aa, a1, UEXC_lcount
	rsr	\aa, LEND
	s32i	\ab, a1, UEXC_lbeg
	s32i	\aa, a1, UEXC_lend
#endif
#if XCHAL_HAVE_MAC16
	rsr	\aa, ACCLO
	rsr	\ab, ACCHI
	s32i	\aa, a1, UEXC_acclo
	s32i	\ab, a1, UEXC_acchi
	rsr	\aa, M0
	rsr	\ab, M1
	s32i	\aa, a1, UEXC_mr + 0
	s32i	\ab, a1, UEXC_mr + 4
	rsr	\aa, M2
	rsr	\ab, M3
	s32i	\aa, a1, UEXC_mr + 8
	s32i	\ab, a1, UEXC_mr + 12
#endif
	.endm

	//  Restore LOOP and MAC16 registers, if configured, from the exception stack
	//  frame pointed to by address register \esf, using \aa, \ab and \ac as temporaries.
	//
	//  Three temp registers are required for this code to be optimal (no interlocks) in
	//  Xtensa LX microarchitectures with 7-stage pipe; otherwise only two
	//  registers would be needed.
	//
	.macro	restore_loops_mac16	esf, aa, ab, ac
#if XCHAL_HAVE_LOOPS
	l32i	\aa, a1, UEXC_lcount
	l32i	\ab, a1, UEXC_lbeg
	l32i	\ac, a1, UEXC_lend
	wsr	\aa, LCOUNT
	wsr	\ab, LBEG
	wsr	\ac, LEND
#endif
#if XCHAL_HAVE_MAC16
	l32i	\aa, a1, UEXC_acclo
	l32i	\ab, a1, UEXC_acchi
	l32i	\ac, a1, UEXC_mr + 0
	wsr	\aa, ACCLO
	wsr	\ab, ACCHI
	wsr	\ac, M0
	l32i	\aa, a1, UEXC_mr + 4
	l32i	\ab, a1, UEXC_mr + 8
	l32i	\ac, a1, UEXC_mr + 12
	wsr	\aa, M1
	wsr	\ab, M2
	wsr	\ac, M3
#endif
	.endm

#endif /* XT_INTERNAL_H */