intdisp.c

uCOS-II ports on Tensilica HiFi330 core.

/* intdisp.c -- Interrupt handlers (called by the interrupt dispatcher)
 *
 * This code is taken from example code in the Xtensa Microprocessor
 * Programmer's Guide.
 *
 * WARNING:  It is highly unlikely that this code works as is on your
 *	particular Xtensa processor configuration.  It is hardcoded
 *	for the specific processor configuration used for the
 *	examples in the Xtensa Microprocessor Programmer's Guide.
 *	(The example code did not use the Xtensa HAL to address this
 *	portability issue, for clarity's sake.)  Getting it to work
 *	on another processor configuration requires some modifications.
 */

/*
 * Copyright (c) 2003-2005 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

#include <xtensa/config/specreg.h>
#include <xtensa/config/core.h>
#include <xtensa/simcall.h>
#include "os_cpu.h"
#include "os_cfg.h"
#include "ucos_ii.h"
#include "timer.h"

int system_ticks;
extern OS_STK *newUserStackPtr;
extern OS_STK *userStackPtr; 
void OSCtxSw(void);

void L1_int0_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 0 */
}

void L1_int1_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 1 */
}

void L1_int2_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 2 */
}

void L1_int3_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 3 */
}

void L1_int4_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 4 */
}

void L1_int5_extlevel()
{
	/* Interrupt handler for Level 1 External Level Triggered Interrupt 5 */
}

void L1_int6_timer0( )
{
	/* Interrupt handler for Level 1 Timer Interrupt 0 */
    unsigned long old_ccompare;
    unsigned long diff;	
	
  /* Since L1 interrupts are disabled and we dont want to incur additional 
   * overhead of calling OSIntEnter
   */
   
	  OSIntNesting++;
	  
	  if (OSIntNesting == 1)
	  {
	  	OSTCBCur->OSTCBStkPtr = userStackPtr;
	  }

    do {
        system_ticks++;
        old_ccompare = read_ccompare0();
        set_ccompare0( old_ccompare + TIMER0_INTERVAL );
        diff = read_ccount() - old_ccompare;
    } while ( diff > TIMER0_INTERVAL );
    
	  OSTimeTick();
	  OSIntExit();
}

void L1_int7_software()
{
	OSIntCtxSw();
    xthal_set_intclear(SOFTWARE0_INT_MASK);

}

void L2_int8_extlevel()
{
	/* Interrupt handler for Level 2 External Level Triggered Interrupt 8 */
}

void L3_int9_extlevel()
{
	/* Interrupt handler for Level 3 External Level Triggered Interrupt 9 */
}

void L3_int10_timer1( )
{
	/* Interrupt handler for Level 3 Timer Interrupt 10 */
    unsigned long old_ccompare;
    unsigned long diff;
    
  /* Since L1 interrupts are disabled and we dont want to incur additional 
   * overhead of calling OSIntEnter
   */
   
	  OSIntNesting++;
	  
	  if (OSIntNesting == 1)
	  {
	  	OSTCBCur->OSTCBStkPtr = userStackPtr;
	  }
  	
    do {
        system_ticks++;
        old_ccompare = read_ccompare1();
        set_ccompare1( old_ccompare + TIMER1_INTERVAL );
        diff = read_ccount() - old_ccompare;
    } while ( diff > TIMER1_INTERVAL );
    
  OSTimeTick();
  OSIntExit();
}

void L3_int11_software()
{
	/* Interrupt handler for Level 3 Software Interrupt */
}
	
void intUnhandled()
{
}