l5v.s

uCOS-II ports on Tensilica HiFi330 core.

/* l5v.S -- Level 5 Interrupt Vector
 *
 * This code is taken from example code in the Xtensa Microprocessor
 * Programmer's Guide.
 *
 * WARNING:  It is highly unlikely that this code works as is on your
 *	particular Xtensa processor configuration.  It is hardcoded
 *	for the specific processor configuration used for the
 *	examples in the Xtensa Microprocessor Programmer's Guide.
 *	(The example code did not use the Xtensa HAL to address this
 *	portability issue, for clarity's sake.)  Getting it to work
 *	on another processor configuration requires some modifications.
 */

/*
 * Copyright (c) 2003-2005 by Tensilica Inc.  ALL RIGHTS RESERVED.
 * These coded instructions, statements, and computer programs are the
 * copyrighted works and confidential proprietary information of Tensilica Inc.
 * They may not be modified, copied, reproduced, distributed, or disclosed to
 * third parties in any manner, medium, or form, in whole or in part, without
 * the prior written consent of Tensilica Inc.
 */

/* 
   Level5InterruptVector (High Priority for Diamond Cores)

   This implements the Level 5 Interrupt (High Priority) vector and transfers
   control to the Level5InterruptHandler.
*/
#include <xtensa/coreasm.h>
#include <xtensa/config/system.h>
#include <xtensa/config/specreg.h>

	.begin literal_prefix .Level5InterruptVector
	.section .Level5InterruptVector.text, "ax"

	.align 4
	.global _Level5InterruptVector	
_Level5InterruptVector:
	wsr     a2, EXCSAVE_5
	movi    a2, _Level5InterruptHandler
	jx      a2
	
		//  If vector too big for allocated space, catch it at assembly time
	//  (albeit with cryptic "can't org backwards" error message):
	.org	XSHAL_INTLEVEL5_VECTOR_SIZE
.Lendlabel:

	.text
	.end	literal_prefix