sja1000.h

基于SJA1000和STC89C54的CAN转RS232透明数据传输

#ifndef   __OCAN__SJA1000_H__
#define   __OCAN__SJA1000_H__

//奇怪，在这边定义 #define unsigned char 会出错？？？

/* BasicCAN mode address map */
unsigned char pdata SJACR	_at_	0x00;	/* Control register */
unsigned char pdata SJACMR	_at_	0x01;	/* Command register */
unsigned char pdata SJASR	_at_	0x02;	/* Status register */
unsigned char pdata SJAIR	_at_	0x03;	/* Interrupt register */
unsigned char pdata SJAACR	_at_	0x04;	/* Acceptance Code register */
unsigned char pdata SJAAMR	_at_	0x05;	/* Acceptance Mask Register */
unsigned char pdata SJABTR0	_at_	0x06;	/* Bus Timing register 0 */
unsigned char pdata SJABTR1	_at_	0x07;	/* Bus Timing register 1 */
unsigned char pdata SJAOCR	_at_	0x08;	/* Output Control register */
unsigned char pdata SJACDR	_at_	0x1f;	/* Clock Divider register */

unsigned char pdata SJATXID1  _at_	0x0a;	/* Identifier byte 1 */
unsigned char pdata SJATXID0  _at_	0x0b;	/* Identifier byte 0 */
unsigned char pdata SJATXDAT0 _at_	0x0c;	/* First data byte */
unsigned char pdata SJATXDAT1 _at_	0x0d;
unsigned char pdata SJATXDAT2 _at_	0x0e;
unsigned char pdata SJATDDAT3 _at_	0x0f;
unsigned char pdata SJATXDAT4 _at_	0x10;
unsigned char pdata SJATXDAT5 _at_	0x11;
unsigned char pdata SJATXDAT6 _at_	0x12;
unsigned char pdata SJATXDAT7 _at_	0x13;

unsigned char pdata SJARXID1  _at_	0x14;	/* Identifier byte 1 */
unsigned char pdata SJARXID0  _at_	0x15;	/* Identifier byte 0 */
unsigned char pdata SJARXDAT0 _at_	0x16;	/* First data byte */
unsigned char pdata SJARXDAT1 _at_	0x17;
unsigned char pdata SJARXDAT2 _at_	0x18;
unsigned char pdata SJARXDAT3 _at_	0x19;
unsigned char pdata SJARXDAT4 _at_	0x1a;
unsigned char pdata SJARXDAT5 _at_	0x1b;
unsigned char pdata SJARXDAT6 _at_	0x1c;
unsigned char pdata SJARXDAT7 _at_	0x1d;

/* Command register */
enum sja1000_BASIC_CMR {
	SJA_CMR_TR  = 1,		    // Transmission request
	SJA_CMR_AT  = (1<<1),		// Abort Transmission
	SJA_CMR_RRB = (1<<2),		// Release Receive Buffer
	SJA_CMR_CDO = (1<<3),		// Clear Data Overrun
	SJA_CMR_GTS = (1<<4)		// Go To Sleep
};
/* Status Register */
enum sja1000_BASIC_SR {
	SJA_SR_RBS = 1,			// Receive Buffer Status
	SJA_SR_DOS = (1<<1),		// Data Overrun Status
	SJA_SR_TBS = (1<<2),		// Transmit Buffer Status
	SJA_SR_TCS = (1<<3),		// Transmission Complete Status
	SJA_SR_RS  = (1<<4),		// Receive Status
	SJA_SR_TS  = (1<<5),		// Transmit Status
	SJA_SR_ES  = (1<<6),		// Error Status
	SJA_SR_BS  = (1<<7)		// Bus Status
};

/* Control Register */
enum sja1000_BASIC_CR {
	SJA_CR_RR  = 1,			// Reset Request
	SJA_CR_RIE = (1<<1),		// Receive Interrupt Enable
	SJA_CR_TIE = (1<<2),		// Transmit Interrupt Enable
	SJA_CR_EIE = (1<<3),		// Error Interrupt Enable
	SJA_CR_OIE = (1<<4)		// Overrun Interrupt Enable
};

/* Interrupt (status) Register */
enum sja1000_BASIC_IR {
	SJA_IR_RI  = 1,			// Receive Interrupt
	SJA_IR_TI  = (1<<1),		// Transmit Interrupt
	SJA_IR_EI  = (1<<2),		// Error Interrupt
	SJA_IR_DOI = (1<<3),		// Data Overrun Interrupt
	SJA_IR_WUI = (1<<4)		// Wake-Up Interrupt
};

/* Clock Divider Register */
enum sja1000_CDR {
	/* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
	SJA_CDR_CLKOUT_MASK = 7,
	SJA_CDR_CLK_OFF = (1<<3),	// Clock Off
	SJA_CDR_RXINPEN = (1<<5),	// TX1 output is RX irq output
	SJA_CDR_CBP = (1<<6),		// Input Comparator By-Pass
	SJA_CDR_PELICAN = (1<<7)	// PeliCAN Mode 
};

/* Output Control Register */
enum sja1000_OCR {
	SJA_OCR_MODE_BIPHASE = 0,
	SJA_OCR_MODE_TEST = 1,
	SJA_OCR_MODE_NORMAL = 2,
	SJA_OCR_MODE_CLOCK = 3,
// TX0 push-pull not inverted
	SJA_OCR_TX0_LH = 0x18,
// TX0 push-pull inverted
	SJA_OCR_TX0_HL = 0x1c,
// TX1 floating (off)
	SJA_OCR_TX1_ZZ = 0,
// TX1 pull-down not inverted
	SJA_OCR_TX1_LZ = 0x40
};

/** Frame format information 0x11 */
enum sja1000_BASIC_ID0 {
	SJA_ID0_RTR = (1<<4),		// Remote request
	SJA_ID0_DLC_M = ((1<<4)-1)	// Length Mask
};

#endif