generic_hal.c

cg编译器

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// generic_hal.c
//

#include <assert.h>
#include <stdio.h>
#include <string.h>

#include "slglobals.h"
#include "generic_hal.h"

#define NUMELS(x) (sizeof(x) / sizeof((x)[0]))

// Static functions
static int InitHAL_generic(slHAL *fHAL);
static int FreeHAL_generic(slHAL *fHAL);
static int RegisterNames_generic(slHAL *fHAL);
static int GetConnectorID_generic(int name);
static int GetConnectorAtom_generic(int name);
static int GetConnectorUses_generic(int cid, int pid);
static int GetConnectorRegister_generic(int cid, int ByIndex, int ratom,
                                        Binding *fBind);
static int GetCapsBit_generic(int bitNumber);
static int CheckInternalFunction_generic(Symbol *fSymb, int *group);
static int BindUniformUnbound_generic(SourceLoc *loc, Symbol *fSymb,
                                      Binding *fBind);
static int BindVaryingSemantic_generic(SourceLoc *loc, Symbol *fSymb,
                                       int semantic, Binding *fBind,
                                       int IsOutVal);
static int PrintCodeHeader_generic(FILE *out);
static int GenerateCode_generic(SourceLoc *loc, Scope *fScope, Symbol *program);
// Static data
#define FLT TYPE_BASE_FLOAT

// These define all the input connector registers for this profile
// you can have numltiple names that refer to the same register number
static ConnectorRegisters inputCRegs_generic[] = {
    { "ATTR0",  0, FLT, REG_AP2V_ATTR0,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR1",  0, FLT, REG_AP2V_ATTR1,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR2",  0, FLT, REG_AP2V_ATTR2,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR3",  0, FLT, REG_AP2V_ATTR3,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR4",  0, FLT, REG_AP2V_ATTR4,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR5",  0, FLT, REG_AP2V_ATTR5,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR6",  0, FLT, REG_AP2V_ATTR6,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR7",  0, FLT, REG_AP2V_ATTR7,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR8",  0, FLT, REG_AP2V_ATTR8,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR9",  0, FLT, REG_AP2V_ATTR9,  4, REG_ALLOC | REG_INPUT, },
    { "ATTR10", 0, FLT, REG_AP2V_ATTR10, 4, REG_ALLOC | REG_INPUT, },
    { "ATTR11", 0, FLT, REG_AP2V_ATTR11, 4, REG_ALLOC | REG_INPUT, },
    { "ATTR12", 0, FLT, REG_AP2V_ATTR12, 4, REG_ALLOC | REG_INPUT, },
    { "ATTR13", 0, FLT, REG_AP2V_ATTR13, 4, REG_ALLOC | REG_INPUT, },
    { "ATTR14", 0, FLT, REG_AP2V_ATTR14, 4, REG_ALLOC | REG_INPUT, },
    { "ATTR15", 0, FLT, REG_AP2V_ATTR15, 4, REG_ALLOC | REG_INPUT, },
};

static ConnectorRegisters outputCRegs_generic[] = {
// These are output register names
    { "HPOS",  0, FLT, REG_V2FR_HPOS,  4, REG_RESERVED | REG_OUTPUT | REG_WRITE_REQUIRED, },
    { "COL0",  0, FLT, REG_V2FR_COL0,  4, REG_RESERVED | REG_OUTPUT, },
    { "COL1",  0, FLT, REG_V2FR_COL1,  4, REG_RESERVED | REG_OUTPUT, },
    { "TEX0",  0, FLT, REG_V2FR_TEX0,  4, REG_ALLOC | REG_OUTPUT, },
    { "TEX1",  0, FLT, REG_V2FR_TEX1,  4, REG_ALLOC | REG_OUTPUT, },
    { "TEX2",  0, FLT, REG_V2FR_TEX2,  4, REG_ALLOC | REG_OUTPUT, },
    { "TEX3",  0, FLT, REG_V2FR_TEX3,  4, REG_ALLOC | REG_OUTPUT, },
    { "FOGC",  0, FLT, REG_V2FR_FOGC,  1, REG_RESERVED | REG_OUTPUT, },
    { "PSIZ",  0, FLT, REG_V2FR_PSIZ,  1, REG_RESERVED | REG_OUTPUT, },
};


// Semantics:
enum { AP2V_GROUP = 0, V2FR_GROUP = 1, };

static SemanticsDescriptor Semantics_generic[] = {
// These are semantics that can be attached to varying variables and
// parameters.  They usually correspond to the input and output registers
// defined above, but don't have to.  You can add multiple names for the
// the same thing as aliases
    // Varying input semantics:
    { "ATTRIB",   FLT, 4, REG_AP2V_ATTR0, 16, AP2V_GROUP, SEM_IN | SEM_VARYING, },
    // Varying output semantics:
    { "POSITION", FLT, 4, REG_V2FR_HPOS, 1, V2FR_GROUP, SEM_OUT | SEM_VARYING, },
    { "FOG",      FLT, 1, REG_V2FR_FOGC, 0, V2FR_GROUP, SEM_OUT | SEM_VARYING, },
    { "COLOR",    FLT, 4, REG_V2FR_COL0, 2, V2FR_GROUP, SEM_OUT | SEM_VARYING, },
    { "PSIZE",    FLT, 1, REG_V2FR_PSIZ, 0, V2FR_GROUP, SEM_OUT | SEM_VARYING, },
    { "TEXCOORD", FLT, 4, REG_V2FR_TEX0, 4, V2FR_GROUP, SEM_OUT | SEM_VARYING, },
};


// These are the connector types which refer to the register names above
static ConnectorDescriptor connectors_generic[] = {
    { CID_GENERIC_IN_NAME,  0, CID_GENERIC_IN_ID,  CONNECTOR_IS_INPUT,  NUMELS(inputCRegs_generic),  inputCRegs_generic  },

    { CID_GENERIC_OUT_NAME, 0, CID_GENERIC_OUT_ID, CONNECTOR_IS_OUTPUT, NUMELS(outputCRegs_generic), outputCRegs_generic },
};


///////////////////////////////////////////////////////////////////////////////
/////////////////////////// Generic output Program ////////////////////////////
///////////////////////////////////////////////////////////////////////////////

/*
 * RegisterProfiles_generic() - Register the profiles supported by this module.
 */

int RegisterProfiles_generic(void)
{
    RegisterProfile(InitHAL_generic, PROFILE_GENERIC_NAME, PROFILE_GENERIC_ID);
    return 1;
} // RegisterProfiles_generic


/*
 * InitHAL_generic()
 */

static int InitHAL_generic(slHAL *fHAL)
{
    /* Initialize functions. */
    fHAL->InitHAL = InitHAL_generic;
    fHAL->FreeHAL = FreeHAL_generic;
    fHAL->RegisterNames = RegisterNames_generic;
    fHAL->GetConnectorID = GetConnectorID_generic;
    fHAL->GetConnectorAtom = GetConnectorAtom_generic;
    fHAL->GetConnectorUses = GetConnectorUses_generic;
    fHAL->GetConnectorRegister = GetConnectorRegister_generic;
    fHAL->GetCapsBit = GetCapsBit_generic;
    fHAL->CheckInternalFunction = CheckInternalFunction_generic;
    fHAL->BindUniformUnbound = BindUniformUnbound_generic;
    fHAL->BindVaryingSemantic = BindVaryingSemantic_generic;
    fHAL->PrintCodeHeader = PrintCodeHeader_generic;
    fHAL->GenerateCode = GenerateCode_generic;

    /* Initialize data. */
    fHAL->vendor = VENDOR_STRING_GENERIC;
    fHAL->version = VERSION_STRING_GENERIC;

    fHAL->semantics = Semantics_generic;
    fHAL->numSemantics = NUMELS(Semantics_generic);

    fHAL->incid = CID_GENERIC_IN_ID;
    fHAL->inputCRegs = inputCRegs_generic;
    fHAL->numInputCRegs = NUMELS(inputCRegs_generic);

    fHAL->outcid = CID_GENERIC_OUT_ID;
    fHAL->outputCRegs = outputCRegs_generic;
    fHAL->numOutputCRegs = NUMELS(outputCRegs_generic);

    fHAL->comment = "//";

    return 1;
} // InitHAL_generic


/*
 * FreeHAL_generic()
 */

static int FreeHAL_generic(slHAL *fHAL)
{
    return 1;
} // FreeHAL_generic


/*
 * RegisterNames_generic()
 */

static int RegisterNames_generic(slHAL *fHAL)
{
    int i, j;

    // Add atoms for connectors and connector registers.
    for (i = 0; i < NUMELS(connectors_generic); i++) {
        ConnectorDescriptor * conn = &connectors_generic[i];
        conn->name = AddAtom(atable, conn->sname);
        for (j = 0; j < conn->numregs; j++)
            conn->registers[j].name = AddAtom(atable, conn->registers[j].sname);
    }

    return 1;
}


/*