📄 ddsfir.mdl
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SourceType "Bus Concatenation AlteraBlockSet"
bwl "8"
bwr "2"
blean off
}
Block {
BlockType Reference
Name "BusConcatenation1"
Ports [2, 1]
Position [105, 166, 210, 204]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "4"
bwr "28"
blean off
}
Block {
BlockType Reference
Name "BusConcatenation2"
Ports [2, 1]
Position [220, 251, 325, 289]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "8"
bwr "20"
blean off
}
Block {
BlockType Reference
Name "BusConversion1"
Ports [1, 1]
Position [475, 386, 550, 404]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Unsigned Integer"
bwl "10"
bwr "0"
Outputs "Unsigned Integer"
obwl "8"
obwr "0"
msb "9"
lsb "2"
rnd off
sat off
}
Block {
BlockType Reference
Name "BusConversion2"
Ports [1, 1]
Position [650, 171, 725, 189]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Unsigned Integer"
bwl "32"
bwr "0"
Outputs "Unsigned Integer"
obwl "10"
obwr "0"
msb "31"
lsb "22"
rnd off
sat off
}
Block {
BlockType Reference
Name "Constant3"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [275, 41, 325, 59]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "2"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "1"
cst "0"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Constant4"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [15, 166, 65, 184]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "4"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "0"
cst "0"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Constant5"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [30, 296, 80, 314]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "20"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "1"
cst "0"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [285, 160, 330, 210]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [540, 165, 585, 215]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "LUT"
Ports [1, 1]
Position [305, 376, 390, 414]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Unsigned Integer"
bwl "10"
bwr "0"
bwaddr "10"
MatlabArray "511*sin( [0:2*pi/(2^10):2*pi] )+512"
LocPin "ddsfirLUT"
lpm off
modulename "d:\\MATLAB701\\work\\DSPBuilder_ddsfir\\ddsfirL"
"UT.lut"
pipeline off
IslibDir "0"
clken off
ena off
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [2, 1]
Position [445, 161, 505, 219]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "++"
pipeline off
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor1"
Ports [2, 1]
Position [765, 151, 825, 209]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "++"
pipeline off
clken off
MaskValue "1"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [970, 349, 1000, 381]
Location [31, 275, 827, 638]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "100"
YMin "0"
YMax "1"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [924, 18, 993, 65]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "d:\\MATLAB701\\work"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Constant
Name "f"
Position [15, 235, 45, 265]
Value "23"
OutDataTypeMode "double"
}
Block {
BlockType Reference
Name "fword"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [65, 242, 130, 258]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "fword"
ppat "d:\\MATLAB701\\work\\DSPBuilder_ddsfir"
nSgCpl "1"
}
Block {
BlockType Constant
Name "p"
Position [15, 70, 45, 100]
Value "45"
OutDataTypeMode "double"
}
Block {
BlockType Reference
Name "pword"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [100, 77, 165, 93]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "pword"
ppat "d:\\MATLAB701\\work\\DSPBuilder_ddsfir"
nSgCpl "1"
}
Block {
BlockType Reference
Name "pword2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [360, 137, 425, 153]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Internal Node"
bwl "32"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "pword2"
ppat "d:\\MATLAB701\\work\\DSPBuilder_ddsfir"
nSgCpl "1"
}
Block {
BlockType Reference
Name "sout"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [680, 382, 745, 398]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "sout"
ppat "d:\\MATLAB701\\work\\DSPBuilder_ddsfir"
nSgCpl "1"
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 5; 95, 0]
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Line {
SrcBlock "f"
SrcPort 1
DstBlock "fword"
DstPort 1
}
Line {
SrcBlock "p"
SrcPort 1
DstBlock "pword"
DstPort 1
}
Line {
SrcBlock "BusConcatenation"
SrcPort 1
Points [200, 0]
DstBlock "Parallel \nAdder Subtractor1"
DstPort 1
}
Line {
SrcBlock "BusConcatenation2"
SrcPort 1
Points [0, -45; -240, 0]
DstBlock "BusConcatenation1"
DstPort 2
}
Line {
SrcBlock "Constant4"
SrcPort 1
DstBlock "BusConcatenation1"
DstPort 1
}
Line {
SrcBlock "BusConcatenation1"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "Delay1"
DstPort 1
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, -40]
Branch {
Points [0, -25; -245, 0]
DstBlock "pword2"
DstPort 1
}
Branch {
Points [25, 0; 0, 30]
DstBlock "BusConversion2"
DstPort 1
}
}
Line {
SrcBlock "pword2"
SrcPort 1
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Line {
SrcBlock "BusConversion2"
SrcPort 1
Points [0, 15]
DstBlock "Parallel \nAdder Subtractor1"
DstPort 2
}
Line {
SrcBlock "Parallel \nAdder Subtractor1"
SrcPort 1
Points [0, 140; -600, 0; 0, 75]
DstBlock "LUT"
DstPort 1
}
Line {
SrcBlock "sout"
SrcPort 1
Points [205, 0]
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "fword"
SrcPort 1
Points [35, 0; 0, 10]
DstBlock "BusConcatenation2"
DstPort 1
}
Line {
SrcBlock "Constant5"
SrcPort 1
Points [60, 0; 0, -25]
DstBlock "BusConcatenation2"
DstPort 2
}
Line {
SrcBlock "pword"
SrcPort 1
Points [0, -15]
DstBlock "BusConcatenation"
DstPort 1
}
Line {
SrcBlock "Constant3"
SrcPort 1
Points [80, 0; 0, 40]
DstBlock "BusConcatenation"
DstPort 2
}
Line {
SrcBlock "BusConversion1"
SrcPort 1
Points [0, -5]
DstBlock "sout"
DstPort 1
}
Line {
SrcBlock "LUT"
SrcPort 1
DstBlock "BusConversion1"
DstPort 1
}
}
}
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